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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AGL400V2-FG144I
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 12/250闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1KB FLASH 400K 144FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 160
绯诲垪锛� IGLOO
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RAM 浣嶇附瑷�(j矛)锛� 55296
杓稿叆/杓稿嚭鏁�(sh霉)锛� 97
闁€鏁�(sh霉)锛� 400000
闆绘簮闆诲锛� 1.14 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 144-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-FPBGA锛�13x13锛�
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IGLOO Low Power Flash FPGAs
Revision 23
2-93
Timing Characteristics
1.5 V DC Core Voltage
Figure 2-22 Input DDR Timing Diagram
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
tDDRICLR2Q1
12
3
4
5
6
7
8
9
CLK
Data
CLR
Out_QR
Out_QF
tDDRICLKQ1
2
4
6
3
5
7
tDDRIHD
tDDRISUD
tDDRICLKQ2
Table 2-164 Input DDR Propagation Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
Std.
Units
tDDRICLKQ1
Clock-to-Out Out_QR for Input DDR
0.48
ns
tDDRICLKQ2
Clock-to-Out Out_QF for Input DDR
0.65
ns
tDDRISUD1
Data Setup for Input DDR (negedge)
0.50
ns
tDDRISUD2
Data Setup for Input DDR (posedge)
0.40
ns
tDDRIHD1
Data Hold for Input DDR (negedge)
0.00
ns
tDDRIHD2
Data Hold for Input DDR (posedge)
0.00
ns
tDDRICLR2Q1
Asynchronous Clear-to-Out Out_QR for Input DDR
0.82
ns
tDDRICLR2Q2
Asynchronous Clear-to-Out Out_QF for Input DDR
0.98
ns
tDDRIREMCLR
Asynchronous Clear Removal Time for Input DDR
0.00
ns
tDDRIRECCLR
Asynchronous Clear Recovery Time for Input DDR
0.23
ns
tDDRIWCLR
Asynchronous Clear Minimum Pulse Width for Input DDR
0.19
ns
tDDRICKMPWH
Clock Minimum Pulse Width High for Input DDR
0.31
ns
tDDRICKMPWL
Clock Minimum Pulse Width Low for Input DDR
0.28
ns
FDDRIMAX
Maximum Frequency for Input DDR
250.00
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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AGL400V2-FG144T 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪: 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:AGL400V2-FG144T - Trays 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:IC FPGA 400K GATES 144FBGA
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