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Fusion Family of Mixed Signal FPGAs
Revision 4
2-179
Timing Characteristics
Table 2-104 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial Temperature Range Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V
Applicable to Pro I/Os
Drive
Strength
Spee
d
Grade tDOUT
tDP
tDIN
tPY
tPYS tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
Std.
0.66
11.01
0.04
1.20
1.57
0.43
11.21
9.05
2.69
2.44
13.45 11.29
ns
鈥�1
0.56
9.36
0.04
1.02
1.33
0.36
9.54
7.70
2.29
2.08
11.44
9.60
ns
鈥�2
0.49
8.22
0.03
0.90
1.17
0.32
8.37
6.76
2.01
1.82
10.04
8.43
ns
8 mA
Std.
0.66
7.86
0.04
1.20
1.57
0.43
8.01
6.44
3.04
3.06
10.24
8.68
ns
鈥�1
0.56
6.69
0.04
1.02
1.33
0.36
6.81
5.48
2.58
2.61
8.71
7.38
ns
鈥�2
0.49
5.87
0.03
0.90
1.17
0.32
5.98
4.81
2.27
2.29
7.65
6.48
ns
12 mA
Std.
0.66
6.03
0.04
1.20
1.57
0.43
6.14
5.02
3.28
3.47
8.37
7.26
ns
鈥�1
0.56
5.13
0.04
1.02
1.33
0.36
5.22
4.27
2.79
2.95
7.12
6.17
ns
鈥�2
0.49
4.50
0.03
0.90
1.17
0.32
4.58
3.75
2.45
2.59
6.25
5.42
ns
16 mA
Std.
0.66
5.62
0.04
1.20
1.57
0.43
5.72
4.72
3.32
3.58
7.96
6.96
ns
鈥�1
0.56
4.78
0.04
1.02
1.33
0.36
4.87
4.02
2.83
3.04
6.77
5.92
ns
鈥�2
0.49
4.20
0.03
0.90
1.17
0.32
4.27
3.53
2.48
2.67
5.94
5.20
ns
24 mA
Std.
0.66
5.24
0.04
1.20
1.57
0.43
5.34
4.69
3.39
3.96
7.58
6.93
ns
鈥�1
0.56
4.46
0.04
1.02
1.33
0.36
4.54
3.99
2.88
3.37
6.44
5.89
ns
鈥�2
0.49
3.92
0.03
0.90
1.17
0.32
3.99
3.50
2.53
2.96
5.66
5.17
ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on