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參數(shù)資料
| 型號： | AFE031AIRGZT |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 32/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AFE POWERLINE COMM 48VQFN |
| 特色產(chǎn)品： | An Intelligent Solar Micro-Inverter Solution |
| 標準包裝： | 1 |
| 位數(shù)： | 10 |
| 通道數(shù)： | 1 |
| 電壓 - 電源，模擬： | 3 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 3 V ~ 3.6 V |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 48-VQFN 裸露焊盤（7x7） |
| 包裝： | 標準包裝 |
| 其它名稱： | 296-29692-6 |
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SBOS531D – AUGUST 2010 – REVISED MAY 2012
Table 14. RESET Register: Address 0x09
Default: 0x00
Reset Register <7:0>
LOCATION
BIT NAME
(0 = LSB)
DEFAULT
R/W
FUNCTION
--
0
--
Reserved
--
1
0
--
Reserved
SOFTRST0,
These bits are used to perform a software reset of the ENABLE1,
SOFTRST1,
2, 3, 4
0, 0, 0
W
ENABLE2, CONTROL2, CONTROL3, and GAIN SELECT
SOFTRST2
registers. Writing '101' to these registers performs a software reset.
This bit is used to indicate the status of a PA thermal overload.
0 = On read, indicates that no thermal overload has occurred since
the last reset.
T_FLAG
5
0
R/W
0 = On write, resets this bit.
1 = On read, indicates that a thermal overload has occurred since
the last reset. Remains latched until reset.
This bit is used to indicate the status of a PA output current
overload.
0 = On read indicates that no current overload has occurred since
I_FLAG
6
0
R/W
the last reset.
0 = On write, resets this bit.
1 = On read indicates that a current overload has occurred since
the last reset. Remains latched until reset.
--
7
0
--
Reserved
Table 15. DieID Register: Address 0x0A
Default: 0x00
DieID Register <7:0>
LOCATION
BIT NAME
(0 = LSB)
DEFAULT
R/W
FUNCTION
DIE ID<0>
0
R
The Die ID register is hard-wired.
DIE ID<1>
1
0
R
The Die ID register is hard-wired.
DIE ID<2>
2
0
R
The Die ID register is hard-wired.
DIE ID<3>
3
0
R
The Die ID register is hard-wired.
DIE ID<4>
4
0
R
The Die ID register is hard-wired.
DIE ID<5>
5
0
R
The Die ID register is hard-wired.
DIE ID<6>
6
0
R
The Die ID register is hard-wired.
DIE ID<7>
7
0
R
The Die ID register is hard-wired.
Table 16. Revision Register: Address 0x0B
Default: 0x02
Revision Register <7:0>
LOCATION
BIT NAME
(0 = LSB)
DEFAULT
R/W
FUNCTION
REVISION ID<0>
0
R
The revision register is hard-wired.
REVISION ID<1>
1
R
The revision register is hard-wired.
REVISION ID<2>
2
0
R
The revision register is hard-wired.
REVISION ID<3>
3
0
R
The revision register is hard-wired.
REVISION ID<4>
4
0
R
The revision register is hard-wired.
REVISION ID<5>
5
0
R
The revision register is hard-wired.
REVISION ID<6>
6
0
R
The revision register is hard-wired.
REVISION ID<7>
7
0
R
The revision register is hard-wired.
38
Copyright 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE031
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