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參數(shù)資料
型號(hào): AFE031AIRGZR
廠商: Texas Instruments
文件頁數(shù): 15/57頁
文件大?。?/td> 0K
描述: IC AFE POWERLINE COMM 48VQFN
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 10
通道數(shù): 1
電壓 - 電源,模擬: 3 V ~ 3.6 V
電壓 - 電源,數(shù)字: 3 V ~ 3.6 V
封裝/外殼: 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-VQFN 裸露焊盤(7x7)
包裝: 帶卷 (TR)
R
= 20 k
SET
W
- 5 kW
1.2 V
I
LIM
(
1
(2
f
)
p
HP
W
20 k
C
=
IN
SBOS531D – AUGUST 2010 – REVISED MAY 2012
The external capacitor, CIN, introduces a single-pole, high-pass characteristic to the PA transfer function;
combined with the inherent low-pass transfer function, this characteristic results in a passband response. The
value of the high-pass cutoff frequency is determined by CIN reacting with the input resistance of the PA circuit,
and can be found from Equation 1:
(1)
Where:
CIN = external input capacitor
fHP = desired high-pass cutoff frequency
For example, setting CIN to 3.3 nF results in a high-pass cutoff frequency of 2.4 kHz. The voltage rating for CIN
should be determined to withstand operation up to the PA power-supply voltage.
When the transmitter is not in use, the output can be disabled and placed into a high-impedance state by writing
a '0' to the PA-OUT bit in the Enable2 Register. Additional power savings can be realized by shutting down the
PA when not in use. Shutting down the PA for power savings is accomplished by writing a '0' to the PA bit in the
Enable1 Register. Shutting down the PA also results in the PA output entering a high-impedance state. When the
PA shuts down, it consumes only 2 mW of power.
The PA_ISET pin (pin 46) provides a resistor-programmable output current limit for the PA block. Equation 2
determines the value of the external RSET resistor attached to this pin.
(2)
Where:
RSET = the value of the external resistor connected between pin 46 and ground.
ILIM = the value of the desired current limit for the PA.
Note that to ensure proper design margin with respect to manufacturing and temperature variations, a 30%
decrease of the value used in Equation 2 for ILIM over the nominal value of ILIM is recommended. See Figure 20,
PA Current Limit vs RSET.
Tx Block
The Tx block consists of the Tx PGA and Tx Filter. The Tx PGA is a low-noise, high-performance, programmable
gain amplifier. In DAC mode (where pin 7 is a logical '1' and Enable1 Register bit location 5 is a logical '1'), the
Tx PGA operates as the internal digital-to-analog converter (DAC) output buffer with programmable gain. In
PWM mode (where pin 7 is a logical '0' and Enable1 Register bit location 5 is a logical '0'), the Tx PGA operates
as a stand-alone programmable gain amplifier. The Tx PGA gain is programmed through the serial interface. The
Tx PGA gain settings are 0.25 V/V, 0.5 V/V, 0.707 V/V, and 1 V/V.
The Tx Filter is a unity-gain, fourth-order low-pass filter. The Tx Filter cutoff frequency is selectable between
CENELEC A or CENELEC B, C, and D modes. The Control1 Register bit location 3 setting (CA CBCD)
determines the cutoff frequency. Setting Control1 Register bit location 3 to '0' selects the CENELEC A band;
setting Control1 Register bit location 3 to '1' selects CENELEC B, C, and D bands.
The AFE031 supports both DAC inputs or PWM inputs for the Tx signal path. DAC mode is recommended for
best performance. In DAC mode, no external components in the Tx signal path are required to meet regulatory
signal emissions requirements. When in DAC mode, the AFE031 accepts serial data from the microprocessor
and writes that data to the internal DAC registers. When in DAC mode (where pin 7 is a logical '1' and Enable1
Register bit location 5 is a logical '1'), the Tx PGA output must be directly coupled to the Tx_FIN1 input and the
unused Tx_FIN2 input must be grounded.
22
Copyright 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE031
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