參數(shù)資料
型號: ADZS-BF548-MPSKIT
廠商: Analog Devices Inc
文件頁數(shù): 59/100頁
文件大?。?/td> 0K
描述: KIT STARTER MULTIMEDIA BF548
產(chǎn)品培訓(xùn)模塊: Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
Multimedia Starter Kit
標(biāo)準(zhǔn)包裝: 1
系列: Blackfin®
類型: DSP:視頻
適用于相關(guān)產(chǎn)品: ADSP-BF548
所含物品: 評估板
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Rev. C
|
Page 61 of 100
|
February 2010
Serial Ports Timing
through Figure 37 on Page 63 describe serial port operations.
Table 41. Serial Ports—External Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSE
TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)
1
3.0
ns
tHFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)1
3.0
ns
tSDRE
Receive Data Setup Before RSCLKx
3.0
ns
tHDRE
Receive Data Hold After RSCLKx
3.0
ns
tSCLKEW
TSCLKx/RSCLKx Width
4.5
ns
tSCLKE
TSCLKx/RSCLKx Period
15.0
ns
tRCLKE
RSCLKx Period
2
11.1
ns
tSUDTE
Start-Up Delay From SPORT Enable To First External TFSx
4
× t
SCLKE
ns
tSUDRE
Start-Up Delay From SPORT Enable To First External RFSx
4
× t
RCLKE
ns
Switching Characteristics
tDFSE
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)3
10.0
ns
tHOFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
3
0.0
ns
tDDTE
Transmit Data Delay After TSCLKx
3
10.0
ns
tHDTE
Transmit Data Hold After TSCLKx3
0.0
ns
1 Referenced to sample edge.
2 For serial port receive with external clock and external frame sync only.
3 Referenced to drive edge.
Table 42. Serial Ports—Internal Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSI
TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)1
10.0
ns
tHFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)1
–1.5
ns
tSDRI
Receive Data Setup Before RSCLKx
10.0
ns
tHDRI
Receive Data Hold After RSCLKx1
–1.5
ns
Switching Characteristics
tDFSI
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
2
3.0
ns
tHOFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2
–1.0
ns
tDDTI
Transmit Data Delay After TSCLKx2
3.0
ns
tHDTI
Transmit Data Hold After TSCLKx
–2.0
ns
tSCLKIW
TSCLKx/RSCLKx Width
4.5
ns
1 Referenced to sample edge.
2 Referenced to drive edge.
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