- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374047 > ADV7343 (Analog Devices, Inc.) Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs PDF資料下載
參數(shù)資料
| 型號： | ADV7343 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs |
| 中文描述： | 六多格式視頻編碼器，11位，297兆赫數(shù)模轉(zhuǎn)換器 |
| 文件頁數(shù)： | 63/88頁 |
| 文件大小： | 1053K |
| 代理商： | ADV7343 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁當(dāng)前第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁
ADV7342/ADV7343
EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL
For timing synchronization purposes, the ADV7342/ADV7343 are able to accept either EAV/SAV time codes embedded in the input
pixel data or external synchronization signals provided on the S_HSYNC, S_VSYNC, P_HSYNC, P_VSYNC, and P_BLANK pins (see
Table 49). It is also possible to output synchronization signals on the S_HSYNC and S_VSYNC pins (see Table 50 to Table 52).
Rev. 0 | Page 63 of 88
Table 49. Timing Synchronization Signal Input Options
Signal
Pin
SD HSYNC In
S_HSYNC
SD VSYNC/FIELD In
S_VSYNC
ED/HD HSYNC In
P_HSYNC
ED/HD VSYNC/FIELD In
P_VSYNC
ED/HD BLANK In
P_BLANK
Condition
SD Slave Timing Mode 1, 2, or 3 Selected (Subaddress 0x8A[2:0]).
1
SD Slave Timing Mode 1, 2, or 3 Selected (Subaddress 0x8A[2:0]).
1
ED/HD Timing Synchronization Inputs Enabled (Subaddress 0x30, Bit 2 = 0).
ED/HD Timing Synchronization Inputs Enabled (Subaddress 0x30, Bit 2 = 0).
1
SD and ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02[7:6] = 00).
Table 50. Timing Synchronization Signal Output Options
Signal
Pin
SD HSYNC Out
S_HSYNC
SD VSYNC/FIELD Out
S_VSYNC
ED/HD HSYNC Out
S_HSYNC
ED/HD VSYNC/FIELD Out
S_VSYNC
Condition
SD Timing Synchronization Outputs Enabled (Subaddress 0x02, Bit 6 = 1).
1
SD Timing Synchronization Outputs Enabled (Subaddress 0x02, Bit 6 = 1).
1
ED/HD Timing Synchronization Outputs Enabled (Subaddress 0x02, Bit 7 = 1).
ED/HD Timing Synchronization Outputs Enabled (Subaddress 0x02, Bit 7 = 1).
1
ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02, Bit 7 = 0).
Table 51. S_HSYNC Output Control
1
ED/HD Input Sync
Format (0x30, Bit 2)
x
x
ED/HD HSYNC
Control
(0x34, Bit 1)
x
x
ED/HD Sync
Output Enable
(0x02, Bit 7)
0
0
SD Sync
Output Enable
(0x02, Bit 6)
0
1
Signal on S_HSYNC Pin
Tristate.
Pipelined SD HSYNC.
Duration
–
See
Appendix 5—
SD Timing
.
As per HSYNC timing.
Same as line blanking
interval.
Same as embedded
HSYNC.
0
1
0
0
1
1
x
x
Pipelined ED/HD HSYNC.
Pipelined ED/HD HSYNC based on
AV Code H bit.
Pipelined ED/HD HSYNC based on
horizontal counter.
x
1
1
x
1
In all ED/HD standards where there is an HSYNC output, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video.
Table 52. S_VSYNC Output Control
1
ED/HD Input
Sync Format
(0x30, Bit 2)
x
x
ED/HD VSYNC
Control
(0x34, Bit 2)
X
X
ED/HD Sync
Output Enable
(0x02, Bit 7)
0
0
SD Sync
Output Enable
(0x02, Bit 6)
0
1
Video Standard
x
Interlaced
Signal on S_VSYNC Pin
Tristate.
Pipelined SD VSYNC
/Field.
Pipelined ED/HD VSYNC
or field signal.
Pipelined field signal
based on AV Code F bit.
Pipelined VSYNC based
on AV Code V bit.
Duration
–
See
Appendix
5—SD Timing
.
As per VSYNC or
field signal timing.
Field.
0
0
1
x
x
1
0
1
x
All HD interlaced
standards
All ED/HD
progressive
standards
All ED/HD
standards
except 525p
525p
1
0
1
x
Vertical blanking
interval.
x
1
1
x
Pipelined ED/HD VSYNC
based on vertical counter.
Aligned with
serration lines.
x
1
1
x
Pipelined ED/HD VSYNC
based on vertical counter.
Vertical blanking
interval.
1
In all ED/HD standards where there is a VSYNC output, the start of the VSYNC pulse is aligned with the falling edge of the embedded VSYNC in the output video.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7344 | Multiformat Video Encoder Six 14-Bit Noise Shaped Video DACs |
| ADV7344BSTZ | Multiformat Video Encoder Six 14-Bit Noise Shaped Video DACs |
| ADV7390 | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7390BCPZ | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7390BCPZ-REEL | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7343BSTZ | 功能描述:IC ENCODER VIDEO W/DAC 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7343WBSTZ | 功能描述:IC ENCODER VID 12BIT DAC 64LQFP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:視頻編碼器 應(yīng)用:DVD，Blu-Ray 電壓 - 電源，模擬:2.6 V ~ 3.46 V 電壓 - 電源，數(shù)字:1.71 V ~ 1.89 V 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商器件封裝:64-LQFP（10x10） 標(biāo)準(zhǔn)包裝:1 |
| ADV7343WBSTZ-RL | 功能描述:Video Encoder IC DVD, Blu-Ray 64-LQFP (10x10) 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 類型:視頻編碼器 應(yīng)用:DVD，Blu-Ray 電壓 - 電源，模擬:2.6 V ~ 3.46 V 電壓 - 電源，數(shù)字:1.71 V ~ 1.89 V 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商器件封裝:64-LQFP（10x10） 標(biāo)準(zhǔn)包裝:1,500 |
| ADV7344 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Video Encoder Six 14-Bit Noise Shaped Video DACs |
| ADV7344BSTZ | 制造商:Analog Devices 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。