參數(shù)資料
型號(hào)： ADV7343
廠商： Analog Devices, Inc.
英文描述： Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs
中文描述： 六多格式視頻編碼器，11位，297兆赫數(shù)模轉(zhuǎn)換器
文件頁(yè)數(shù)： 44/88頁(yè)
文件大?。?/td> 1053K
代理商： ADV7343
ADV7342/ADV7343
INPUT CONFIGURATION
The ADV7342/ADV7343 support a number of different input
modes. The desired input mode is selected using Subaddress
0x01, Bits[6:4]. The ADV7342/ADV7343 default to standard
definition only (SD only) upon power-up. Table 31 provides an
overview of all possible input configurations. Each input mode
is described in detail in the following sections.
STANDARD DEFINITION ONLY
Subaddress 0x01, Bits[6:4] = 000
Standard definition (SD) YCrCb data can be input in 4:2:2 format.
Standard definition (SD) RGB data can be input in 4:4:4 format.
A 27 MHz clock signal must be provided on the CLKIN_A pin.
Input synchronization signals are provided on the S_HSYNC
and S_VSYNC pins.
8-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0; Subaddress 0x88, Bit 3 = 0
In 8-bit 4:2:2 YCrCb input mode, the interleaved pixel data is
input on Pin S7 to Pin S0 (or Pin Y7 to Pin Y0, depending on
Rev. 0 | Page 44 of 88
Subaddress 0x01, Bit 7), with S0/Y0 being the LSB. The ITU-R
BT.601/656 input standard is supported.
16-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0; Subaddress 0x88, Bit 3 = 1
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on
Pin S7 to Pin S0 (or Pin Y7 to Pin Y0, depending on Subaddress
0x01, Bit 7), with S0/Y0 being the LSB.
The CrCb pixel data is input on Pin Y7 to Pin Y0 (or Pin C7 to
Pin C0, depending on Subaddress 0x01, Bit 7), with Y0/C0
being the LSB.
24-Bit 4:4:4 RGB Mode
Subaddress 0x87, Bit 7 = 1
In 24-bit 4:4:4 RGB input mode, the red pixel data is input on
Pin S7 to Pin S0, the green pixel data is input on Pin Y7 to
Pin Y0, and the blue pixel data is input on Pin C7 to Pin C0.
S0, Y0, and C0 are the respective bus LSBs.
Table 31. Input Configuration
Input Mode
1
000
SD Only
8-Bit YCrCb
2
16-Bit YCrCb
2,
3
8-Bit YCrCb
2
16-Bit YCrCb
2,
3
24-Bit RGB
3
001
ED/HD-SDR Only
4, 5
16-Bit YCrCb
24-Bit YCrCb
24-Bit RGB
3
010
ED/HD-DDR Only (8-Bit)
5
011
SD and ED/HD-SDR (24-Bit)
5
100
SD and ED/HD-DDR (16-Bit)
5
111
ED Only (54 MHz) (8-Bit)
5
1
The input mode is determined by Subaddress 0x01, Bits[6:4].
2
In SD only (YCrCb) mode, the format of the input data is determined by Subaddress 0x88, Bits[4:3]. See Table 26 for more information.
3
External synchronization signals must be used in this input mode. Embedded EAV/SAV timing codes are not supported.
4
In ED/HD-SDR only (YCrCb) mode, the format of the input data is determined by Subaddress 0x33, Bit 6. See Table 19 for more information.
5
ED = enhanced definition = 525p and 625p.
S
Y
C
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Y/C/S Bus Swap (0x01[7]) = 0
CrCb
Y/C/S Bus Swap (0x01[7]) = 1
YCrCb
Y
SD RGB Input Enable (0x87[7]) = 1
G
ED/HD RGB Input Enable (0x35[1]) = 0
Y
Y
ED/HD RGB Input Enable (0x35[1]) = 1
G
YCrCb
Y (ED/HD)
YCrCb (ED/HD)
YCrCb
YCrCb
Y
CrCb
R
B
CrCb
Cb
Cr
R
B
YCrCb (SD)
YCrCb (SD)
CrCb (ED/HD)
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