參數(shù)資料
型號(hào)： ADV7343
廠商： Analog Devices, Inc.
英文描述： Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs
中文描述： 六多格式視頻編碼器，11位，297兆赫數(shù)模轉(zhuǎn)換器
文件頁(yè)數(shù)： 45/88頁(yè)
文件大小： 1053K
代理商： ADV7343
ADV7342/ADV7343
Rev. 0 | Page 45 of 88
MPEG2
DECODER
CLKIN_A
S[7:0] OR Y[7:0]*
27MHz
YCrCb
ADV7342/
ADV7343
*SELECTED BY SUBADDRESS 0x01, BIT 7.
Figure 51. SD Only Example Application
S_VSYNC,
S_HSYNC
2
10
0
ENHANCED DEFINITION/HIGH DEFINITION ONLY
Subaddress 0x01, Bits[6:4] = 001 or 010
Enhanced definition (ED) or high definition (HD) YCrCb data
can be input in either 4:2:2 or 4:4:4 formats. If desired, dual data
rate (DDR) pixel data inputs can be employed (4:2:2 format only).
Enhanced definition (ED) or high definition (HD) RGB data
can be input in 4:4:4 format (single data rate only).
The clock signal must be provided on the CLKIN_A pin. Input
synchronization signals are provided on the P_HSYNC,
P_VSYNC, and P_BLANK pins.
16-Bit 4:2:2 YCrCb Mode (SDR)
Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 1
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is
input on Pin Y7 to Pin Y0, with Y0 being the LSB.
The CrCb pixel data is input on Pin C7 to Pin C0, with C0
being the LSB.
8-Bit 4:2:2 YCrCb Mode (DDR)
Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 1
In 8-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is input
on Pin Y7 to Pin Y0 upon either the rising or falling edge of
CLKIN_A. Y0 is the LSB.
The CrCb pixel data is also input on Pin Y7 to Pin Y0
upon the opposite edge of CLKIN_A. Y0 is the LSB.
Whether the Y data is clocked in upon the rising or falling edge
of CLKIN_A is determined by Subaddress 0x01, Bits[2:1] (see
Figure 52 and Figure 53).
3FF
00
00
X
Y
Y0
Y1
Cr0
CLKIN_A
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.
Y[7:0]
Cb0
0
Figure 52. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
3FF
00
00
XY
Cb0
Cr0
Y1
CLKIN_
A
Y[7:0]
Y0
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO11 IN THIS CASE.
0
Figure 53. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
24-Bit 4:4:4 YCrCb Mode
Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 0
In 24-bit 4:4:4 YCrCb input mode, the Y pixel data is input on
Pin Y7 to Pin Y0, with Y0 being the LSB.
The Cr pixel data is input on Pin S7 to Pin S0, with S0 being
the LSB.
The Cb pixel data is input on Pin C7 to Pin C0, with C0 being
the LSB.
24-Bit 4:4:4 RGB Mode
Subaddress 0x35, Bit 1 = 1
In 24-bit 4:4:4 RGB input mode, the red pixel data is input on
Pin S7 to Pin S0, the green pixel data is input on Pin Y7 to Pin
Y0, and the blue pixel data is input on Pin C7 to Pin C0. S0, Y0,
and C0 are the respective bus LSBs.
MPEG2
DECODER
CLKIN_
A
C[7:0]
S[7:0]
Y[7:0]
INTERLACED TO
PROGRESSIVE
YCrCb
P_VSYNC,
P_HSYNC,
P_BLANK
10
Cb
10
Cr
10
Y
3
0
ADV7342/
ADV7343
Figure 54. ED/HD Only Example Application
SIMULTANEOUS STANDARD DEFINITION AND
ENHANCED DEFINITION/HIGH DEFINITION
Subaddress 0x01, Bits[6:4] = 011 or 100
The ADV7342/ADV7343 are able to simultaneously process SD
4:2:2 YCrCb data and ED/HD 4:2:2 YCrCb data. The 27 MHz
SD clock signal must be provided on the CLKIN_A pin. The
ED/HD clock signal must be provided on the CLKIN_B pin. SD
input synchronization signals are provided on the S_HSYNC
and S_VSYNC pins. ED/HD input synchronization signals are
provided on the P_HSYNC, P_VSYNC and P_BLANK pins.
SD 8-Bit 4:2:2 YCrCb and ED/HD-SDR 16-Bit 4:2:2 YCrCb
The SD 8-bit 4:2:2 YCrCb pixel data is input on Pin S7 to Pin
S0, with S0 being the LSB.
The ED/HD 16-bit 4:2:2 Y pixel data is input on Pin Y7 to Pin
Y0, with Y0 being the LSB.
The ED/HD 16-bit 4:2:2 CrCb pixel data is input on Pin C7 to
Pin C0, with C0 being the LSB.
SD 8-Bit 4:2:2 YCrCb and ED/HD-DDR 8-Bit 4:2:2 YCrCb
The SD 8-bit 4:2:2 YCrCb pixel data is input on Pin S7 to Pin
S0, with S0 being the LSB.
The ED/HD-DDR 8-bit 4:2:2 Y pixel data is input on Pin Y7 to
Pin Y0 upon the rising or falling edge of CLKIN_B. Y0 is the LSB.
The ED/HD-DDR 8-bit 4:2:2 CrCb pixel data is also input on Pin
Y7 to Pin Y0 upon the opposite edge of CLKIN_B. Y0 is the LSB.
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