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參數(shù)資料
| 型號： | ADV7341BSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Multiformat Video Encoder, Six 12-Bit Noise Shaped Video㈢ DACS |
| 中文描述： | SERIAL INPUT LOADING, 12-BIT DAC, PQFP64 |
| 封裝： | ROHS COMPLIANT, MS-026BCD, LQFP-64 |
| 文件頁數(shù)： | 57/88頁 |
| 文件大?。?/td> | 1066K |
| 代理商： | ADV7341BSTZ |
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ADV7340/ADV7341
DOUBLE BUFFERING
Subaddress 0x33, Bit 7 for ED/HD,
Subaddress 0x88, Bit 2 for SD
Double-buffered registers are updated once per field. Double
buffering improves overall performance because modifications
to register settings are not made during active video, but take
effect prior to the start of the active video on the next field.
Double buffering can be activated on the following ED/HD
registers using Subaddress 0x33, Bit 7: ED/HD Gamma A and
Gamma B curves, and ED/HD CGMS registers.
Double buffering can be activated on the following SD registers
using Subaddress 0x88, Bit 2: SD Gamma A and Gamma B
curves, SD Y scale, SD Cr scale, SD Cb scale, SD brightness, SD
closed captioning, and SD Macrovision Bits[5:0] (Subaddress
0xE0, Bits[5:0]).
PROGRAMMABLE DAC GAIN CONTROL
Subaddress 0x0A to Subaddress 0x0B
It is possible to adjust the DAC output signal gain up or down
from its absolute level. This is illustrated in Figure 69.
DAC 4 to DAC 6 are controlled by Register 0x0A.
DAC 1 to DAC 3 are controlled by Register 0x0B.
Rev. 0 | Page 57 of 88
CASE B
700mV
300mV
NEGATIVE GAIN PROGRAMMED IN
DAC OUTPUT LEVEL REGISTERS,
SUBADDRESS 0x0A, 0x0B
CASE A
GAIN PROGRAMMED IN DAC OUTPUT LEVEL
REGISTERS, SUBADDRESS 0x0A, 0x0B
700mV
300mV
0
Figure 69. Programmable DAC Gain—Positive and Negative Gain
In Case A of Figure 69, the video output signal is gained. The
absolute level of the sync tip and blanking level both increase
with respect to the reference video output signal. The overall
gain of the signal is increased from the reference signal.
In Case B of Figure 69, the video output signal is reduced. The
absolute level of the sync tip and blanking level both decrease
with respect to the reference video output signal. The overall
gain of the signal is reduced from the reference signal.
The range of this feature is specified for ±7.5% of the nominal
output from the DACs. For example, if the output current of the
DAC is 4.33 mA, the DAC gain control feature can change this
output current from 4.008 mA (7.5%) to 4.658 mA (+7.5%).
The reset value of the control registers is 0x00, that is, nominal
DAC current is output. Table 46 is an example of how the
output current of the DACs varies for a nominal 4.33 mA
output current.
Table 46. DAC Gain Control
Reg. 0x0A or
Reg.0x0B
0100 0000 (0x40)
0011 1111 (0x3F)
0011 1110 (0x3E)
...
...
0000 0010 (0x02)
0000 0001 (0x01)
0000 0000 (0x00)
DAC
Current
(mA)
4.658
4.653
4.648
...
...
4.43
4.38
4.33
% Gain
7.5000%
7.3820%
7.3640%
...
...
0.0360%
0.0180%
0.0000%
Note
Reset value,
nominal
1111 1111 (0xFF)
1111 1110 (0xFE)
...
...
1100 0010 (0xC2)
1100 0001 (0xC1)
1100 0000 (0xC0)
GAMMA CORRECTION
Subaddress 0x44 to Subaddress 0x57 for ED/HD,
Subaddress 0xA6 to Subaddress 0xB9 for SD
Generally, gamma correction is applied to compensate for the
nonlinear relationship between signal input and output
brightness level (as perceived on a CRT). It can also be applied
wherever nonlinear processing is used.
Gamma correction uses the function
Signal
OUT
= (
Signal
IN
)
γ
where γ = is the gamma correction factor.
Gamma correction is available for SD and ED/HD video. For
both variations, there are 20, 8-bit registers. They are used to
program the Gamma Correction Curve A and Gamma
Correction Curve B.
ED/HD gamma correction is enabled using Subaddress 0x35,
Bit 5. ED/HD Gamma Correction Curve A is programmed at
Subaddress 0x44 to Subaddress 0x4D, and ED/HD Gamma
Correction Curve B is programmed at Subaddress 0x4E to
Subaddress 0x57.
4.25
4.23
...
...
4.018
4.013
4.008
0.0180%
0.0360%
...
...
7.3640%
7.3820%
7.5000%
相關PDF資料 |
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| ADV7341EBZ | Multiformat Video Encoder, Six 12-Bit Noise Shaped Video㈢ DACS |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7341EBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Video Encoder, Six 12-Bit Noise Shaped Video㈢ DACS |
| ADV7342 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs |
| ADV7342BSTZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs |
| ADV7343 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs |
| ADV7343BSTZ | 功能描述:IC ENCODER VIDEO W/DAC 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
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