參數(shù)資料
型號: ADV7322KSTZ1
廠商: Analog Devices, Inc.
英文描述: Multiformat 11-Bit HDTV Video Encoder
中文描述: 多格式11位高清晰度電視視頻編碼器
文件頁數(shù): 8/88頁
文件大?。?/td> 991K
代理商: ADV7322KSTZ1
ADV7322
Preliminary Technical Data
TIMING SPECIFICATIONS
V
AA
= 2.375 V 2.625 V, V
DD
= 2.375 V 2.625 V, V
DD_IO
= 2.375 V 3.6 V, V
REF
= 1.235 V, R
SET
= 3040 , R
LOAD
= 300 . All specifications
T
MIN
to T
MAX
(0°C to 70°C), unless otherwise noted.
Table 4.
Parameter
Min
Typ
Max
Unit
MPU PORT
1
SCLOCK Frequency
0
400
kHz
SCLOCK High Pulse Width, t
1
0.6
μs
SCLOCK Low Pulse Width, t
2
1.3
μs
Hold Time (Start Condition), t
3
0.6
μs
Rev. PrA | Page 8 of 88
Test Conditions
First clock generated after this period relevant
for repeated start condition
SD PAL square pixel mode
PS/HD async mode
SD [2×, 16×]
SD component mode [16×]
PS [1×]
PS [8×]
HD [2×, 1×]
Setup Time (Start Condition), t
4
Data Setup Time, t
5
SDATA, SCLOCK Rise Time, t
6
SDATA, SCLOCK Fall Time, t
7
Setup Time (Stop Condition), t
8
RESET Low Time
ANALOG OUTPUTS
Analog Output Delay
2
Output Skew
CLOCK CONTROL AND PIXEL PORT
3
f
CLK
f
CLK
Clock High Time, t
9
Clock Low Time, t
10
Data Setup Time, t
111
Data Hold Time, t
121
SD Output Access Time, t
13
SD Output Hold Time, t
14
HD Output Access Time, t
13
HD Output Hold Time, t
14
PIPELINE DELAY
4
0.6
100
0.6
100
40
40
2.0
2.0
5.0
5.0
7
1
81
63
76
35
41
36
300
300
29.5
15
14
μs
ns
ns
ns
μs
ns
ns
ns
MHz
MHz
% of one clk cycle
% of one clk cycle
ns
ns
ns
ns
ns
ns
clk cycles
clk cycles
clk cycles
clk cycles
clk cycles
1
Guaranteed by characterization.
2
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
3
Data: C[9:0]; Y[9:0], S[9:0]
Control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, S_VSYNC, S_BLANK
4
SD, PS = 27 MHz, HD = 74.25 MHz.
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