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ADV7322
Preliminary Technical Data
TABLE OF CONTENTS
Specifications.....................................................................................6
Rev. PrA | Page 2 of 88
Dynamic Specifications...................................................................7
Timing Specifications.......................................................................8
Timing Diagrams..............................................................................9
Absolute Maximum Ratings..........................................................17
Thermal Characteristics............................................................17
Pin Configuration and Function Descriptions...........................18
Typical Performance Characteristics...........................................20
MPU Port Description...................................................................24
Register Access................................................................................26
Register Programming...............................................................26
Subaddress Register (SR7 to SR0)............................................26
Input Configuration.......................................................................39
Standard Definition Only..........................................................39
Progressive Scan Only or HDTV Only ...................................39
Simultaneous Standard Definition and Progressive Scan or
HDTV..........................................................................................39
Progressive Scan at 27 MHz (Dual Edge) or 54 MHz...........40
Features............................................................................................42
Output Configuration................................................................42
HD Async Timing Mode...........................................................43
HD Timing Reset........................................................................44
SD Real-Time Control, Subcarrier Reset, and Timing Reset 44
Reset Sequence............................................................................46
SD VCR FF/RW Sync.................................................................46
Vertical Blanking Interval .........................................................47
Subcarrier Frequency Registers................................................47
Square Pixel Timing Mode........................................................48
Filters............................................................................................49
Color Controls and RGB Matrix..............................................50
Programmable DAC Gain Control..........................................54
Gamma Correction....................................................................54
HD Sharpness Filter and Adaptive Filter Controls................ 56
HD Sharpness Filter and Adaptive Filter Application
Examples...................................................................................... 57
SD Digital Noise Reduction...................................................... 58
Coring Gain Border................................................................... 59
Coring Gain Data....................................................................... 59
DNR Threshold.......................................................................... 59
Border Area................................................................................. 59
Block Size Control...................................................................... 59
DNR Input Select Control......................................................... 59
DNR Mode Control................................................................... 60
Block Offset Control.................................................................. 60
SD Active Video Edge................................................................ 60
SAV/EAV Step Edge Control.................................................... 60
Board Design and Layout.............................................................. 62
DAC Termination and Layout Considerations...................... 62
Video Output Buffer and Optional Output Filter.................. 62
PCB Board Layout...................................................................... 63
Appendix 1—Copy Generation Management System .............. 65
PS CGMS..................................................................................... 65
HD CGMS................................................................................... 65
SD CGMS.................................................................................... 65
Function of CGMS Bits............................................................. 65
CGMS Functionality.................................................................. 65
Appendix 2—SD Wide Screen Signaling..................................... 68
Appendix 3—SD Closed Captioning........................................... 69
Appendix 4—Test Patterns............................................................ 70
Appendix 5—SD Timing Modes.................................................. 73
Mode 0 (CCIR-656)—Slave Option (Timing Register 0 TR0 =
X X X X X 0 0 0)......................................................................... 73
Mode 0 (CCIR-656)—Master Option (Timing Register 0 TR0
= X X X X X 0 0 1)...................................................................... 74