參數(shù)資料
型號： ADV7322KSTZ1
廠商： Analog Devices, Inc.
英文描述： Multiformat 11-Bit HDTV Video Encoder
中文描述： 多格式11位高清晰度電視視頻編碼器
文件頁數(shù)： 44/88頁
文件大?。?/td> 991K
代理商： ADV7322KSTZ1
ADV7322
Preliminary Technical Data
HD TIMING RESET
A timing reset is achieved by toggling the HD timing reset control
bit [Subaddress 0x14, Bit 0] from 0 to 1. In this state the horizontal
and vertical counters will remain reset. When this bit is set back to
0, the internal counters will commence counting again.
Rev. PrA | Page 44 of 88
The minimum time the pin has to be held high is one clock
cycle; otherwise, this reset signal might not be recognized. This
timing reset applies to the HD timing counters only.
SD REAL-TIME CONTROL, SUBCARRIER RESET,
AND TIMING RESET
[Subaddress 0x44, Bits 2 and 1]
Together with the RTC_SCR_TR pin and SD Mode Register 3
[Address 0x44, Bits 1 and 2], the ADV7322 can be used in (a)
timing reset mode, (b) subcarrier phase reset mode, or (c) RTC
mode.
a.
A timing reset is achieved in a low-to-high transition
on the RTC_SCR_TR pin (Pin 31). In this state, the
horizontal and vertical counters will remain reset.
Upon releasing this pin (set to low), the internal
counters will commence counting again, the field
count will start on Field 1, and the subcarrier phase
will be reset.
The minimum time the pin must be held high is one
clock cycle; otherwise, this reset signal might not be
recognized. This timing reset applies to the SD timing
counters only.
b.
In subcarrier phase reset, a low-to-high transition on
the RTC_SCR_TR pin (Pin 31) will reset the
subcarrier phase to zero on the field following the
subcarrier phase reset when the SD RTC/TR/SCR
control bits at Address 0x44 are set to 01.
This reset signal must be held high for a minimum of
one clock cycle.
Since the field counter is not reset, it is recommended
that the reset signal is applied in Field 7 [PAL] or Field
3 [NTSC]. The reset of the phase will then occur on
the next field, i.e., Field 1, being lined up correctly with
the internal counters. The field count register at
Address 0x7B can be used to identify the number of
the active field.
c.
In RTC mode, the ADV7322 can be used to lock to an
external video source. The real-time control mode
allows the ADV7322 to automatically alter the
subcarrier frequency to compensate for line length
variations. When the part is connected to a device that
outputs a digital data stream in the RTC format, such
as an ADV7183A video decoder (see Figure 61), the
part will automatically change to the compensated
subcarrier frequency on a line by line basis. This
digital data stream is 67 bits wide and the subcarrier is
contained in Bits 0 to 21. Each bit is two clock cycles
long. Write 0x00 into all four subcarrier frequency
registers when this mode is used.
DISPLAY
NO TIMING RESET APPLIED
TIMING RESET APPLIED
START OF FIELD 4 OR 8
F
SC
PHASE = FIELD 4 OR 8
F
SC
PHASE = FIELD 1
TIMING RESET PULSE
307
310
307
1
2
3
4
5
6
7
21
313
320
DISPLAY
START OF FIELD 1
0
Figure 59. Timing Reset Timing Diagram
相關PDF資料
PDF描述
ADV7400 ADV7402/ADV7400 Multiformat Video Decoders for Advanced TV
ADV7400KST-110 ADV7402/ADV7400 Multiformat Video Decoders for Advanced TV
ADV7400KST-140 ADV7402/ADV7400 Multiformat Video Decoders for Advanced TV
ADV7400KST-80 ADV7402/ADV7400 Multiformat Video Decoders for Advanced TV
ADV7402 ADV7402/ADV7400 Multiformat Video Decoders for Advanced TV
相關代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7324 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs
ADV7324KSTZ 制造商:Analog Devices 功能描述:Video Encoder 64-Pin LQFP
ADV7330 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat 11-Bit Triple DAC Video Encoder
ADV73305502 制造商:LG Corporation 功能描述:FRAME ASSEMBLY
ADV73306701 制造商:LG Corporation 功能描述:Frame Assembly
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*