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參數(shù)資料
| 型號： | ADV7310 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs |
| 中文描述： | 多格式視頻編碼器216兆赫六噪聲整形的12位DAC |
| 文件頁數(shù)： | 65/84頁 |
| 文件大?。?/td> | 1099K |
| 代理商： | ADV7310 |
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REV. A
ADV7310/ADV7311
–65–
The following register settings are used to generate an SD NTSC
CVBS output on DAC A:
Register
Setting
Subaddress
00h
40h
42h
44h
4Ah
80h
10h
40h
40h
08h
All other registers are set as normal/default.
For PAL CVBS output on DAC A, the same settings are used
except that subaddress = 40h and register setting = 11h.
The following register settings are used to generate an SD NTSC
black bar pattern output on DAC A:
Register
Setting
Subaddress
00h
02h
40h
42h
44h
4Ah
80h
04h
10h
40h
40h
08h
All other registers are set as normal/default.
For PAL black bar pattern output on DAC A, the same settings
are used except that subaddress = 40h and register setting = 11h.
The following register settings are used to generate a 525p hatch
pattern on DAC D:
Register
Setting
Subaddress
00h
01h
10h
11h
16h
17h
18h
10h
10h
40h
05h
A0h
80h
80h
All other registers are set as normal/default.
For 625p hatch pattern on DAC D, the same register settings
are used except that subaddress = 10h and register setting = 50h.
For a 525p black bar pattern output on DAC D, the same settings
are used as above except that subaddress = 02h and register
setting = 24h.
For 625p black bar pattern output on DAC D, the same settings
are used as above except that subaddress = 02h and register
setting = 24h; and subaddress = 10h and register setting = 50h.
相關(guān)PDF資料 |
PDF描述 |
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| ADV7310KST | Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs |
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| ADV7311KST | Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs |
| ADV7312 | Multiformat 11-Bit HDTV Video Encoder |
| ADV7312KST | Multiformat 11-Bit HDTV Video Encoder |
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| ADV73107005 | 制造商:LG Corporation 功能描述:Frame Assembly |
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