參數(shù)資料
型號: ADV7310
廠商: Analog Devices, Inc.
英文描述: Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
中文描述: 多格式視頻編碼器216兆赫六噪聲整形的12位DAC
文件頁數(shù): 18/84頁
文件大?。?/td> 1099K
代理商: ADV7310
REV. A
–18–
ADV7310/ADV7311
SR7–
SR0
00h
Register
Power Mode
Register
Bit Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
Register Setting
Sleep Mode off
Sleep Mode on
Register Reset Values
(Shaded)
FCh
0
1
PLL on
PLL off
0
1
DAC F off
DAC F on
DAC E off
DAC E on
DAC D off
DAC D on
DAC D off
DAC C on
DAC B off
DAC B on
DAC A off
DAC A on
Disabled
Enabled
Cb clocked on rising edge
Y clocked on rising edge
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reserved
Clock Align
0
0
1
Must be set if the phase
delay between the two input
clocks is <9.25 ns or
>27.75 ns.
SD input only
PS input only
HDTV input only
SD and PS [20-bit]
SD and PS [10-bit]
SD and HDTV [SD
oversampled]
SD and HDTV [HDTV
oversampled]
PS only [at 54 MHz]
10-bit data on S bus
10-bit data on Y bus
Only if two input clocks are used
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
38h
1
1
0
1
1
1
Y/S Bus Swap
0
1
Only for PS dual edge clk mode
SD Mode 10-bit/20-bit Modes
DAC B: Power On/Off
DAC A: Power On/Off
BTA T-1004 or BT.1362
Compatibility
Clock Edge
Only for PS interleaved input at
27 MHz
Input Mode
Mode Select
Register
01h
Sleep Mode. With this
control enabled, the
current consumption is
reduced to
μ
A level. All
DACs and the internal
PLL cct are disabled. I
2
C
registers can be read from
and written to in Sleep
Mode.
PLL and Oversampling
Control. This control
allows the internal PLL cct
to be powered down and
the over-sampling to be
switched off.
DAC F: Power On/Off
DAC E: Power On/Off
DAC D: Power On/Off
DAC C: Power On/Off
相關(guān)PDF資料
PDF描述
ADV7310KST Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
ADV7311 Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
ADV7311KST Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
ADV7312 Multiformat 11-Bit HDTV Video Encoder
ADV7312KST Multiformat 11-Bit HDTV Video Encoder
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