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參數(shù)資料
| 型號： | ADV7310 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs |
| 中文描述： | 多格式視頻編碼器216兆赫六噪聲整形的12位DAC |
| 文件頁數(shù)： | 37/84頁 |
| 文件大?。?/td> | 1099K |
| 代理商： | ADV7310 |
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REV. A
ADV7310/ADV7311
–37–
LCC1
GLL
P19–P10
ADV7183A
VIDEO
DECODER
COMPOSITE
VIDEO
1
CLKIN_A
RTC_SCR_TR
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
Y9-Y0/S9–S0
RTC
LOW
COUNT START
128
TIME SLOT 01
13
0
14 BITS
SUBCARRIER
PHASE
14
21
19
F
SC
PLL INCREMENT
2
VALID
SAMPLE
INVALID
SAMPLE
8/LINE
LOCKED
CLOCK
6768
4 BITS
RESERVED
0
SEQUENCE
BIT
3
RESET
BIT
4
RESERVED
5 BITS
RESERVED
ADV7310/
ADV7311
NOTES
1
i.e., VCR OR CABLE
2
F
SC
PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7310/ADV7311 F
SC
DDS REGISTER IS F
SC
PLL INCREMENTS BITS 21:0
PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS
OF THE ADV7310/ADV7311.
SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
4
RESET ADV7310/ADV7311 DDS
SELECTED BY REGISTER ADDRESS 0x01 BIT 7
5
5
Figure 32. RTC Timing and Connections
XXXXXX
XXXXXX
OFF
DIGITAL TIMING SIGNALS SUPPRESSED
VALID VIDEO
TIMING ACTIVE
RESET
DIGITAL TIMING
DACs
A, B, C
PIXEL DATA
VALID
Figure 33.
RESET
Timing Sequence
Reset Sequence
A reset is activated with a high-to-low transition on the
RESET
pin [Pin 33] according to the timing specifications. The ADV7310/
ADV7311 will revert to the default output configuration.
Figure 32 illustrates the
RESET
sequence timing.
SD VCR FF/RW Sync
[Subaddress 42h, Bit 5]
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit can be used for non-
standard input video, i.e., in fast forward or rewind modes.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct num-
ber of lines/fields are reached; in rewind mode, this sync signal
usually occurs after the total number of lines/fields are reached.
Conventionally this means that the output video will have cor-
rupted field signals, one generated by the incoming video and
one generated when the internal lines/field counters reach the
end of a field.
When the VCR FF/RW sync control is enabled [Subaddress 42h
Bit 5] the lines/field counters are updated according to the
incoming
VSYNC
signal and the analog output matches the
incoming
VSYNC
signal.
This control is available in all slave timing modes except Slave
Mode 0.
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