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參數(shù)資料
| 型號： | ADV7300A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs |
| 中文描述： | 多格式統(tǒng)計，逐行掃描/ HDTV視頻編碼器與六噪聲整形⑩12位DAC |
| 文件頁數(shù)： | 29/68頁 |
| 文件大?。?/td> | 1544K |
| 代理商： | ADV7300A |
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REV. A
ADV7300A/ADV7301A
–29–
INPUT AND OUTPUT CONFIGURATION
STANDARD DEFINITION ONLY
The 8- or 10-bit multiplexed input data is input on Pins S9–S0,
with S0 being the LSB in 10-bit Input Mode. For 8-bit Input
Mode, the data is input on Pins S9–S2. ITU-R.BT601/ITU-
R.BT656 input standards are supported. In 16-bit Input Mode,
the Y pixel data is input on Pins S9–S2 and CrCb data on
Pins Y9–Y2. In 20-bit Input Mode, the Y pixel data is input on
S9–S0 and CrCb pixel data on Pins Y9–Y0. The 27 MHz clock
input must be input on Pin CLKIN_A. Input sync signals
are optional and are input on the
S_VSYNC
,
S_HSYNC
,
and
S_BLANK
pins.
MPEG2
DECODER
S_VSYNC
S_HSYNC
S_BLANK
CLKIN_A
S9–S0
27MHz
3
10
YCrCb
ADV7300A/
ADV7301A
Figure 20. Standard Definition Only Input Mode
PROGRESSIVE SCAN ONLY OR HDTV ONLY
YCrCb Progressive Scan, HDTV, or any other HD YCrCb data
can be input in 4:2:2 or 4:4:4 format. In 4:2:2 Input Mode, the
Y data is input on Pins Y9–Y0 and the CrCb data on Pins C9–
C0. In 4:4:4 Input Mode, Y data is input on Pins Y9–Y0, Cb
data on Pins C9–C0, and Cr data on Pins S9–S0. If the
YCrCb data does not conform to SMPTE293M (525 p), ITU-
R.BT1358M (625 p), SMPTE274M (1080 i), SMPTE296M
(720 p), or BTA-T1004, the Async Timing Mode must be used.
RGB data can only be input in 4:4:4 format in PS Input Mode
only, or HDTV Input Mode only, when HD RGB input is
enabled. G data is input on Pins Y9–Y0, R data on S9–S0, and
B data on Pins C9–C0. The clock signal must be input on Pin
CLKIN_A. Synchronization signals are optional and are input on
Pins
P_VSYNC
,
P_HSYNC
, and P_BLANK.
MPEG2
DECODER
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_A
S9–S0
10
Cr
C9–C0
Y9–Y0
INTERLACED
TO
PROGRESSIVE
YCrCb
10
Cb
10
Y
3
27MHz
ADV7300A/
ADV7301A
Figure 21. Progressive Scan Only Input Mode
SIMULTANEOUS STANDARD DEFINITION AND
PROGRESSIVE SCAN OR HDTV
YCrCb PS, HDTV, or any other HD data must be input in 4:2:2
format. In 4:2:2 Input Mode, the Y data is input on Pins Y9–Y0
and the CrCb data on C9–C0. If PS 4:2:2 data is interleaved onto
a single 10-bit bus, Pins Y9–Y0 are used for the Input Port. The
interleaved data is to be input at 27 MHz in setting the Input Mode
Register at Address 01h accordingly. If the YCrCb data does not
conform to SMPTE293M (525 p), ITU-R.BT1358M (625 p),
SMPTE274M (1080 i), SMPTE296M (720 p), or BTA-T1004,
the Async Timing Mode must be used.
The 8- or 10-bit standard definition data must be compliant to
ITU-R.BT601/ITU-R.BT656 in 4:2:2 format. Standard definition
data is input on Pins S9–S0, with S0 being the LSB. Using 8-bit input
format, the data is input on Pins S9–S2. The clock input for SD must
be input on CLKIN_A, and the clock input for HD must be input
on CLKIN_B. Synchronization signals are optional. SD syncs are
input on Pins
S_VSYNC
,
S_HSYNC
, and
S_BLANK
; the
HD syncs on Pins
P_VSYNC
,
P_HSYNC
, and P_BLANK.
MPEG2
DECODER
S_VSYNC
S_HSYNC
S_BLANK
CLKIN_A
C9–C0
10
CrCb
Y9–Y0
INTERLACED
TO
PROGRESSIVE
YCrCb
10
Y
3
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_B
3
27MHz
S9–S0
10
27MHz
ADV7300A/
ADV7301A
Figure 22. Simultaneous Progressive Scan and SD Input
S_VSYNC
S_HSYNC
S_BLANK
CLKIN_A
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_B
SDTV
DECODER
3
27MHz
8
YCrCb
HDTV
DECODER
8
CrCb
8
Y
3
74MHz
1080 i
720 p
ADV7300A/
ADV7301A
S9–S2
C9–C2
Y9–Y2
Figure 23. Simultaneous HDTV and SD Input
If in Simultaneous Input Mode the two clock phases differ by less
than 9.25 ns or more than 27.75 ns, the Clock Align Bit must be
set accordingly. This also applies if the Pixel Align Bit is set. If
the application uses the same clock source for both SD and PS,
the Clock Align Bit must be set since the phase difference
between both inputs is less than 9.25 ns.
t
DELAY
t
DELAY
9.25ns OR
27.75ns
Figure 24. Clock Phase with Two Input Clocks
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7300AKST | Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs |
| ADV7301A | Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs |
| ADV7301AKST | Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs |
| ADV7302A | 32X2 SHROUDED VERT. HDR |
| ADV7302AKST | Sand Paper; Abrasive Grade:A VFN; Color:Maroon; Pack Quantity:6; Roll Length:30ft; Width:2" |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7300AKST | 制造商:Analog Devices 功能描述: |
| ADV7301A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs |
| ADV7301AKST | 功能描述:IC DAC VIDEO HDTV 6-12BIT 64LQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV73025702 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV73025801 | 制造商:LG Corporation 功能描述:Frame Assembly |
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