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REV. 0
ADV7196A
–30–
DAC TERMINATION AND LAYOUT CONSIDERATIONS
Voltage Reference
The ADV7196A contains an on-board voltage reference. The
V
REF
pin is normally terminated to
V
AA
through a 0.1
μ
F capacitor
when the internal
V
REF
is used. Alternatively, the ADV7196A
can be used with an external
V
REF
(AD589).
Resistor
R
SET
is connected between the
R
SET
pin and AGND and
is used to control the full-scale output current and therefore the
DAC voltage output levels. For full-scale output
R
SET
must have
a value of 2470
.
R
LOAD
has a value of 300
. When an input
range of 0–1023 is selected the value of
R
SET
must be 2820
.
The ADV7196A has three analog outputs, corresponding to Y, Pr,
Pb video signals. The DACs must be used with external buffer circuits
in order to provide sufficient current to drive an output device.
Suitable op amps are the AD8009, AD8002, AD8001, or AD8057.
To calculate the output full-scale current and voltage the follow-
ing equations should be used:
V
OUT
=
I
OUT
R
LOAD
I
OUT
=
[
V
REF
k
]
/R
SE
T
where:
k = 5.66 [for input ranges 64–940, 64–960, output standards
EIA770.1–3]
k = 6.46 [for input ranges 0–1023, output standard RS–170/343A]
V
REF
= 1.235 V
PC BOARD LAYOUT CONSIDERATIONS
The ADV7196A is optimally designed for lowest noise performance,
both radiated and conducted noise. To complement the excellent
noise performance of the ADV7196A, it is imperative that great
care be given to the PC board layout.
The layout should be optimized for lowest noise on the ADV7196A
power and ground lines. This can be achieved by shielding the
digital inputs and providing good decoupling. The lead length
between groups of
V
AA
and AGND and
V
DD
and DGND pins
should be kept as short as possible to minimized inductive ringing.
It is recommended that a four-layer printed circuit board is used.
With power and ground planes separating the layer of the signal
carrying traces of the components and solder side layer. Placement
of components should consider to separate noisy circuits, such
as crystal clocks, high-speed logic circuitry and analog circuitry.
There should be a separate analog ground plane (AGND) and
a separate digital ground plane (GND).
Power planes should encompass a digital power plane (V
DD
) and
a analog power plane (V
AA
). The analog power plane should contain
the DACs and all associated circuitry, and the
V
REF
circuitry.
The digital power plane should contain all logic circuitry. The analog
and digital power planes should be individually connected to the
common power plane at one single point through a suitable filter-
ing device, such as a ferrite bead.
300
5k
5k
MPU BUS
4.7k
V
DD
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
ALSB
DV
RESET
CLKIN
R
SET
SDA
SCL
DAC A
V
DD
VSYNC
/TSYNC
ADV7196A
UNUSED
INPUTS
SHOULD BE
GROUNDED
DAC B
100
HSYNC
/
SYNC
DAC C
27MHz, 74.25MHz OR
74.1758MHz CLOCK
4.7k
4.7 F
6.3V
300
300
100
2.47k OR
2.82k
10nF
0.1 F
Y OUTPUT
Pr (V) OUTPUT
Pb (U) OUTPUT
V
REF
GND
13, 52
AGND
26, 33
Y0
–
Y9
Cr0
–
Cr9
Cb/Cr0
–
Cb/Cr9
0.1 F
10nF
0.1 F
24, 35
1, 12
V
DD
V
AA
COMP
V
AA
V
AA
V
DD
V
DD
V
DD
Figure 57. Circuit Layout