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參數(shù)資料
| 型號： | ADV7196A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision |
| 中文描述： | 多格式逐行掃描/高清晰度電視編碼器三種11位DAC，10位數(shù)據(jù)輸入，以及Macrovision |
| 文件頁數(shù)： | 28/36頁 |
| 文件大小： | 501K |
| 代理商： | ADV7196A |
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REV. 0
ADV7196A
–28–
MODE REGISTER 2
MR1 (MR27–MR20)
(Address (SR4–SR0) = 02H)
Figure 53 shows the various operations under the control of Mode
Register 2.
MR2 BIT DESCRIPTION
Y Delay (MR20–MR22)
With these bits it is possible to delay the Y signal with respect to
the falling edge of the horizontal sync signal by up to four pixel
clock cycles. Figure 52 demonstrates this facility.
Color Delay (MR23–MR25)
With theses bits it is possible to delay the color signals with respect
to the falling edge of the horizontal sync signal by up to four pixel
clock cycles. Figure 52 demonstrates this facility.
Reserved (MR26–MR27)
A “0” must be written to these bits
.
MAX DELAY
NO DELAY
NO DELAY
MAX DELAY
PrPb DELAY
Y DELAY
Y OUTPUT
PrPb OUTPUTS
Figure 52. Y and Color Delay
MODE REGISTER 3
MR3 (MR37–MR30)
(Address (SR4-SR0) = 03H)
Figure 54 shows the various operations under the control of Mode
Register 3
.
MR3 BIT DESCRIPTION
HDTV Enable (MR30)
When this bit is set to “1” the ADV7196A reverts to HDTV
mode. When set to “0” the ADV7196A reverts to Progressive
Scan mode (PS mode).
Reserved (MR31–MR32)
A “0” must be written to these bits.
DAC A Control (MR33)
Setting this bit to “1” enables DAC A, otherwise this DAC is
powered down.
DAC B Control (MR34)
Setting this bit to “1” enables DAC B, otherwise this DAC is
powered down.
DAC C Control (MR35)
Setting this bit to “1” enables DAC C, otherwise this DAC is
powered down.
Reserved (MR36–MR37)
A “0” must be written to these bits.
MR21
MR27
MR22
MR24
MR25
MR23
MR20
MR26
MR25
0
0
0
0
1
MR24
0
0
1
1
0
MR23
0
1
0
1
0
0 PCLK
1 PCLK
2 PCLK
3 PCLK
4 PCLK
COLOR DELAY
MR22
0
0
0
0
1
MR21
0
0
1
1
0
MR20
0
1
0
1
0
0 PCLK
1 PCLK
2 PCLK
3 PCLK
4 PCLK
Y DELAY
MR27
–
MR26
ZERO MUST BE
WRITTEN TO
THESE BITS
Figure 53. Mode Register 2
MR37
MR32
MR34
MR36
ZERO MUST BE
WRITTEN TO
THESE BITS
MR37
–
MR36
MR34
0
1
POWER-DOWN
NORMAL
DAC B CONTROL
MR35
MR35
0
1
POWER-DOWN
NORMAL
DAC C CONTROL
MR33
ZERO MUST BE
WRITTEN TO
THESE BITS
MR32
–
MR31
MR31
MR30
0
1
DISABLE
ENABLE
HDTV ENABLE
MR30
MR33
0
1
POWER-DOWN
NORMAL
DAC A CONTROL
Figure 54. Mode Register 3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7196AKS | Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision |
| ADV7197 | Multiformat HDTV Encoder with Three 11-Bit DACs |
| ADV7197KST | Multiformat HDTV Encoder with Three 11-Bit DACs |
| ADV7304A | Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV 14-Bit DACs |
| ADV7304AKST | Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV 14-Bit DACs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7196AKS | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision |
| ADV7197 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat HDTV Encoder with Three 11-Bit DACs |
| ADV7197KS | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:MULTI-FORMAT HDTV ENCODER, 3 11-BIT DACS - Bulk |
| ADV7197KST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat HDTV Encoder with Three 11-Bit DACs |
| ADV7197KSZ | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:MULTI-FORMAT HDTV ENCODER, 3 11-BIT DACS - Bulk |
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