參數(shù)資料
型號(hào): ADV7196
廠商: Analog Devices, Inc.
英文描述: Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision
中文描述: 多格式逐行掃描/高清晰度電視編碼器三種11位DAC,10位數(shù)據(jù)輸入,以及Macrovision
文件頁數(shù): 5/36頁
文件大?。?/td> 501K
代理商: ADV7196
REV. 0
–5–
ADV7196A
3.3 V TIMING–SPECIFICATIONS
P
arameter
Min
Typ
Max
Unit
Conditions
MPU PORT
1
SCLOCK Frequency
SCLOCK High Pulsewidth, t
1
SCLOCK Low Pulsewidth, t
2
Hold Time (Start Condition), t
3
Setup Time (Start Condition), t
4
Data Setup Time, t
5
SDATA, SCLOCK Rise Time, t
6
SDATA, SCLOCK Fall Time, t
7
Setup Time (Stop Condition), t
8
Reset Low Time
0
0.6
1.3
0.6
0.6
100
400
kHz
μ
s
μ
s
μ
s
μ
s
ns
ns
ns
μ
s
ns
After This Period the 1st Clock Is Generated
Relevant for Repeated Start Condition
300
300
0.6
100
ANALOG OUTPUTS
Analog Output Delay
2
Analog Output Skew
10
0.5
ns
ns
CLOCK CONTROL AND PIXEL PORT
3
f
CLK
f
CLK
f
CLK
Clock High Time t
9
Clock Low Time t
10
Data Setup Time t
11
Data Hold Time t
12
Control Setup Time t
11
Control Hold Time t
12
Pipeline Delay
Pipeline Delay
27
74.25
81
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
Clock Cycles
Clock Cycles
Progressive Scan Mode
HDTV Mode
Async Timing Mode and
1
×
Interpolation
5.0
5.0
2.0
4.5
7.0
4.0
16
29
1.5
2.0
For 4:4:4 Pixel Input Format at
1
×
Oversampling
For 4:4:4 or 4:2:2 Pixel Input Format at
2
×
Oversampling
NOTES
1
Guaranteed by characterization.
2
Output delay measured from 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
3
Data: Cb/Cr [9–0], Cr [9–0], Y [9:0]
Control:
HSYNC
/
SYNC
,
VSYNC
/TSYNC, DV
Specifications subject to change without notice.
(V
AA
= 3.15 V to 3.45 V, V
REF
= 1.235 V, R
SET
= 2470 , R
LOAD
= 300 . All specifications
T
MIN
to T
MAX
(0 C to 70 C) unless otherwise noted.)
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