參數(shù)資料
型號(hào): ADV7196
廠商: Analog Devices, Inc.
英文描述: Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision
中文描述: 多格式逐行掃描/高清晰度電視編碼器三種11位DAC,10位數(shù)據(jù)輸入,以及Macrovision
文件頁(yè)數(shù): 23/36頁(yè)
文件大?。?/td> 501K
代理商: ADV7196
REV. 0
ADV7196A
–23–
ADAPTIVE FILTER GAIN 1
AFG1 (AFG1)7–0
(Address (SR5–SR0) = 22H)
This 8-bit-wide register is used to program the gain applied to signals
which lie above Adaptive Filter Threshold A but are smaller than
Adaptive Filter Threshold B.
Gain A and Gain B values vary from –8 to +7. The individual
responses are shown in the figures below.
Settings for (AFG1)3–0 have no effect unless Adaptive Mode Con-
trol is set to Mode B (MR56 = “1”).
AFG13
AFG10
GAIN A
AFG17
AFG16
AFG15
AFG14
AFG13
AFG12
AFG11
AFG10
AFG17
AFG14
GAIN B
Figure 38. Adaptive Filter Gain 1 Register
ADAPTIVE FILTER GAIN 2
AFG2 (AFG2)7–0
(Address (SR5–SR0) = 23H)
This 8-bit-wide register is used to program the gain applied
to signals which lie above Adaptive Filter Threshold B but are
smaller than Adaptive Filter Threshold C.
Gain A and Gain B values vary from –8 to +7. The individual
responses are shown in the figures below.
Settings for (AFG2)3–0 have no effect unless Adaptive Mode Con-
trol is set to Mode B (MR56 = “1”).
AFG23
AFG20
GAIN A
AFG27
AFG26
AFG25
AFG24
AFG23
AFG22
AFG21
AFG20
AFG27
AFG24
GAIN B
Figure 39. Adaptive Filter Gain 2 Register
ADAPTIVE FILTER GAIN 3
AFG3 (AFG3)7–0
(Address (SR5–SR0) = 24H)
This 8-bit-wide register is used to program the gain applied to signals
which lie above Adaptive Filter Threshold C
Gain A and Gain B values vary from –8 to +7. The individual
responses are shown in the figures below.
Settings for (AFG3)3–0 have no effect unless Adaptive Mode Con-
trol is set to Mode B (MR56 = “1”).
The gain applied to signals which lie below Adaptive Threshold A
are programmed in the Filter Gain register.
At any one time only one of the following registers is active: AFG1,
AFG2, AFG3, FG. The gain values can be preprogrammed and
become active whenever the threshold conditions for the accord-
ing register is met. To program the Adaptive Filter Gain registers
the source register settings are used as for the Filter Gain register
.
AFG33
AFG30
GAIN A
AFG37
AFG36
AFG35
AFG34
AFG33
AFG32
AFG31
AFG30
AFG37
AFG34
GAIN B
Figure 40. Adaptive Filter Gain 3 Register
ADAPTIVE FILTER THRESHOLD A
AFTA (AFTA)7–0
(Address (SR5–SR0) = 25H)
This 8-bit-wide register is used to program the threshold value for
small edges. The recommended programmable threshold range is
from 16–235, although any value in the range of 0–255 can be used.
AFTA7
AFTA0
ADAPTIVE FILTER
THRESHOLD A
AFTA7
AFTA6
AFTA5
AFTA4
AFTA3
AFTA2
AFTA1
AFTA0
Figure 41. Adaptive Filter Threshold A Register
ADAPTIVE FILTER THRESHOLD B
AFTB (AFTB)7–0
(Address (SR5–SR0) = 26H)
This 8-bit-wide register is used to program the threshold value for
medium edges and has priority over Adaptive Threshold A. The
recommended programmable threshold range is from 16–235,
although any value in the range of 0–255 can be used.
AFTB7
AFTB0
ADAPTIVE FILTER
THRESHOLD B
AFTB7
AFTB6
AFTB5
AFTB4
AFTB3
AFTB2
AFTB1
AFTB0
Figure 42. Adaptive Filter Threshold B Register
ADAPTIVE FILTER THRESHOLD C
AFTC (AFTC)7–0
(Address (SR5–SR0) = 27H)
This 8-bit-wide register is used to program the threshold value
for large edges and has priority over Adaptive Threshold A and B.
The recommended programmable threshold range is from 16–235,
although any value in the range of 0–255 can be used.
AFTC7
AFTC0
ADAPTIVE FILTER
THRESHOLD C
AFTC7
AFTC6
AFTC5
AFTC4
AFTC3
AFTC2
AFTC1
AFTC0
Figure 43. Adaptive Filter Threshold C Register
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