參數(shù)資料
型號(hào)： ADV7191
廠商： Analog Devices, Inc.
英文描述： Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs
中文描述： 視頻編碼器與六10位DAC和DAC的輸出6視頻編碼器
文件頁(yè)數(shù)： 40/69頁(yè)
文件大?。?/td> 628K
代理商： ADV7191
ADV7190/ADV7191
–40–
REV. 0
Sharpness CONTROL REGISTER (PR)
(Address (SR5–SR0) = 22H)
The sharpness response register is an 8-bit-wide register. The
four MSBs are set to 0. The four LSBs are written to in order to
select a desired
fi
lter response. Figure 76 shows the operation
under control of this register.
PR BIT DESCRIPTION
Sharpness Response Value (PR3–PR0)
These four bits are used to select the desired luma
fi
lter response.
The option of twelve responses is given supporting a gain boost/
attenuation in the range
–
4 dB to +4 dB. The value 12 (1100)
written to these four bits corresponds to a boost of +4 dB while
the value 0 (0000) corresponds to
–
4 dB. For normal operation
these four bits are set to 6 (0110).
Note: Luma Filter Select has to be set to Extended Mode and
Sharpness Filter Enable Control has to be enabled for settings
in the Sharpness Control Register to take effect (MR02
–
04 =
100; MR74 = 1). See Internal Filter Response section.
Reserved (PR4–PR7)
A Logic 0 must be written to these bits.
PR3
–
PR0
SHARPNESS
RESPONSE VALUE
ZERO MUST BE
WRITTEN TO
THESE BITS
PR7
–
PR4
PR7
PR6
PR5
PR4
PR3
PR2
PR1
PR0
Figure 76. Sharpness Control Register
DNR REGISTERS 2–0
(DNR 2–DNR 0)
(Address (SR5–SR0) = 23H–25H)
The Digital Noise Reduction Registers are three 8-bit wide
register. They are used to control the DNR processing. See
Digital Noise Reduction section.
Coring Gain Border (DNR00–DNR03)
These four bits are assigned to the gain factor applied to border
areas.
In DNR Mode the range of gain values is 0
–
1, in increments of
1/8. This factor is applied to the DNR
fi
lter output which lies
below the set threshold range. The result is then subtracted
from the original signal.
In DNR Sharpness Mode the range of gain values is 0
–
0.5, in
increments of 1/16. This factor is applied to the DNR
fi
lter out-
put which lies above the threshold range.
The result is added to the original signal.
Coring Gain Data (DNR04–DNR07)
These four bits are assigned to the gain factor applied to the luma
data inside the MPEG pixel block.
In DNR Mode the range of gain values is 0
–
1, in increments of
1/8. This factor is applied to the DNR
fi
lter output which lies
below the set threshold range. The result is then subtracted
from the original signal.
In DNR Sharpness Mode the range of gain values is 0
–
0.5, in
increments of 1/16. This factor is applied to the DNR
fi
lter out-
put which lies above the threshold range. The result is added to
the original signal.
Figures 77 and 78 show the various operations under the control
of DNR Register 0.
DNR07
DNR06
DNR05
DNR04
DNR03
DNR02
DNR01
DNR00
CORING GAIN DATA
DNR DNR DNR DNR
07 06 05 04
0 0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1/16
2/16
3/16
4/16
5/16
6/16
7/16
8/16
CORING GAIN BORDER
DNR DNR DNR DNR
03 02 01 00
0 0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1/16
2/16
3/16
4/16
5/16
6/16
7/16
8/16
Figure 77. DNR Register 0 in Sharpness Mode
CORING GAIN DATA
DNR DNR DNR DNR
07 06 05 04
0 0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1/8
2/8
3/8
4/8
5/8
6/8
7/8
1
CORING GAIN BORDER
DNR DNR DNR DNR
03 02 01 00
0 0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1/8
2/8
3/8
4/8
5/8
6/8
7/8
1
DNR07
DNR06
DNR05
DNR04
DNR03
DNR02
DNR01
DNR00
Figure 78. DNR Register 0 in DNR Mode
D
NR1 BIT DESCRIPTION
DNR Threshold (DNR10–DNR15)
These six bits are used to de
fi
ne the threshold value in the range
of 0 to 63. The range is an absolute value.
Border Area (DNR16)
In setting DNR16 to a Logic 1 the block transition area can be
de
fi
ned to consist of four pixels. If this bit is set to a Logic 0 the
border transition area consists of two pixels, where one pixel
refers to two clock cycles at 27 MHz.
Block Size Control (DNR17)
This bit is used to select the size of the data blocks to be processed
(see Figure 79). Setting the block size control function to a
Logic 1 de
fi
nes a 16
×
16 pixel data block, a Logic 0 de
fi
nes an
8
×
8 pixel data block, where one pixel refers to two clock cycles
at 27 MHz.
720 485 PIXELS
(NTSC)
2 PIXEL
PIX8 8
PIX8 8
Figure 79. MPEG Block Diagram
相關(guān)PDF資料
PDF描述
ADV7191KST Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs
ADV7190 Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs
ADV7192KST Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs
ADV7192 Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs
ADV7194KST Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7191KST 制造商:Analog Devices 功能描述:Video Encoder 6DAC 10-Bit 64-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:54M 4X STD DEF ENCODER NON-MACRO I.C. - Tape and Reel
ADV7191KSTZ 制造商:Analog Devices 功能描述:Video Encoder 6DAC 10-Bit 64-Pin LQFP 制造商:Analog Devices 功能描述:IC VIDEO ENCODER
ADV7192 制造商:AD 制造商全稱:Analog Devices 功能描述:Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs
ADV7192KST 制造商:AD 制造商全稱:Analog Devices 功能描述:Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs
ADV7194 制造商:AD 制造商全稱:Analog Devices 功能描述:Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling
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