參數資料
型號: ADV7191
廠商: Analog Devices, Inc.
英文描述: Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs
中文描述: 視頻編碼器與六10位DAC和DAC的輸出6視頻編碼器
文件頁數: 36/69頁
文件大小: 628K
代理商: ADV7191
ADV7190/ADV7191
–36–
REV. 0
SUBCARRIER FREQUENCY REGISTERS 3–0
(FSC31–FSC0) (Address (SR4–SR0) = 0CH–0FH)
These 8-bit-wide registers are used to set up the Subcarrier Fre-
quency. The value of these registers are calculated by using the
following equation:
Register
=
(
Subcarrier Frequency
f
f
SCF
CLK
)
×
2
1
32
Example
:
NTSC Mode, f
CLK
= 27
MHz
,
f
SCF
= 3.5795454
MHz
=
(
Subcarrier Frequency alue
V
)
×
×
×
2
1
3 5795454
.
10
27
10
32
6
6
Subcarrier Register Value =
21F07C16
Hex
Figure 62 shows how the frequency is set up by the four registers.
FSC31
FSC30
FSC29
FSC28
FSC27
FSC26
FSC25
FSC24
SUBCARRIER
FREQUENCY
REG 3
FSC23
FSC22
FSC21
FSC20
FSC19
FSC18
FSC17
FSC16
SUBCARRIER
FREQUENCY
REG 2
SUBCARRIER
FREQUENCY
REG 1
FSC7
FSC6
FSC5
FSC4
FSC3
FSC2
FSC1
FSC0
SUBCARRIER
FREQUENCY
REG 0
FSC15
FSC14
FSC13
FSC12
FSC11
FSC10
FSC9
FSC8
Figure 62. Subcarrier Frequency Registers
SUBCARRIER PHASE REGISTER (FPH7–FPH0)
(Address (SR4–SR0) = 10H)
This 8-bit-wide register is used to set up the Subcarrier Phase.
Each bit represents 1.41
°
. For normal operation this register is
set to 00Hex.
FPH7
FPH6
FPH5
FPH4
FPH3
FPH2
FPH1
FPH0
SUBCARRIER
PHASE
REGISTER
Figure 63. Subcarrier Phase Register
CLOSED CAPTIONING EVEN FIELD
DATA REGISTER 1–0 (CCD15–CCD0)
(Address (SR4–SR0) = 11–12H)
These 8-bit-wide registers are used to set up the closed captioning
extended data bytes on Even Fields. Figure 64 shows how the
high and low bytes are set up in the registers.
CCD15
CCD14
CCD13
CCD12
CCD11
CCD10
CCD9
CCD8
BYTE 1
CCD7
CCD6
CCD5
CCD4
CCD3
CCD2
CCD1
CCD0
BYTE 0
Figure 64. Closed Captioning Extended Data Register
CLOSED CAPTIONING ODD FIELD
DATA REGISTER 1–0 (CED15–CED0)
(Subaddress (SR4–SR0) = 13–14H)
These 8-bit-wide registers are used to set up the closed captioning
data bytes on Odd Fields. Figure 65 shows how the high and low
bytes are set up in the registers.
CED15
CED14
CED13
CED12
CED11
CED10
CED9
CED8
BYTE 1
CED7
CED6
CED5
CED4
CED3
CED2
CED1
CED0
BYTE 0
Figure 65. Closed Captioning Data Register
TR17
TR16
TR15
TR14
TR13
TR12
TR11
TR10
TR17 TR16
0 0 0 T
PCLK
0
1
1
0
1
1
1 T
PCLK
2 T
PCLK
3 T
PCLK
HSYNC
TO PIXEL
DATA ADJUST
TR15 TR14 T
C
0 T
B
1
T
B
+ 32 s
HSYNC
TO
VSYNC
RISING EDGE DELAY
(MODE 1 ONLY)
TR13 TR12 T
B
0 0 0 T
PCLK
0
1
1
0
1
1
4 T
PCLK
8 T
PCLK
18 T
PCLK
HSYNC
TO
VSYNC
DELAY
TR11 TR10 T
A
0 0 1 T
PCLK
0
1
1
0
1
1
4 T
PCLK
16 T
PCLK
128 T
PCLK
HSYNC
WIDTH
TR15 TR14
0 0 1 T
PCLK
0
1
1
0
1
1
4 T
PCLK
16 T
PCLK
128 T
PCLK
VSYNC
WIDTH
(MODE 2 ONLY)
LINE 313
LINE 314
LINE 1
T
B
T
A
T
C
VSYNC
HSYNC
TIMING MODE 1 (MASTER/PAL)
Figure 61. Timing Register 1
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