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參數(shù)資料
| 型號： | ADV7191 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs |
| 中文描述： | 視頻編碼器與六10位DAC和DAC的輸出6視頻編碼器 |
| 文件頁數(shù)： | 18/69頁 |
| 文件大?。?/td> | 628K |
| 代理商： | ADV7191 |
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ADV7190/ADV7191
–18–
REV. 0
In DNR Mode, if the absolute value of the filter output is smaller
than the threshold, it is assumed to be noise. A programmable
amount (Coring Gain Control) of this noise signal will be sub-
tracted from the original signal.
In DNR Sharpness Mode, if the absolute value of the filter output
is less than the programmed threshold, it is assumed to be noise,
as before. Otherwise, if the level exceeds the threshold, now
being identified as a valid signal, a fraction of the signal (Coring
Gain Control) will be added to the original signal in order to boost
high frequency components and to sharpen the video image.
In MPEG systems it is common to process the video information
in blocks of 8
×
8 pixels for MPEG2 systems, or 16
×
16 pixels for
MPEG1 systems (Block Size Control). DNR can be applied to
the resulting block transition areas that are known to contain
noise. Generally the block transition area contains two pixels.
It is possible to define this area to contain four pixels (Border
Area Control).
It is also possible to compensate for variable block positioning or
differences in YCrCb pixel timing with the use of the (Block Offset
Control). See Figure 82 for further information (Mode Register
8, DNR Registers 0–2.)
DOUBLE BUFFERING
Double buffering can be enabled or disabled on the following
registers: Closed Captioning Registers, Brightness Control,
V Scale, U Scale, Contrast Control, Hue Adjust, the Gamma
Curve Select bit, and Macrovision Registers. These registers are
updated once per field on the falling edge of the
VSYNC
signal.
Double buffering improves the overall performance of the
ADV7190/ADV7191, since modifications to register settings
will not be made during active video, but take effect on the
start of the active video. (Mode Register 8.)
GAMMA CORRECTION CONTROL
Gamma correction may be performed on the luma data. The
user has the choice to use either of two different gamma curves,
A or B. At any one time one of these curves is operational if
gamma correction is enabled. Gamma correction allows the
mapping of the luma data to a user-defined function. (See Gamma
Correction Registers 0–13 section.) (Mode Register 8, Gamma
Correction Registers 0–13.)
NTSC PEDESTAL CONTROL
In NTSC mode it is possible to have the pedestal signal gener-
ated on the output video signal. (Mode Register 2.)
POWER-ON
RESET
After power-up, it is necessary to execute a
RESET
operation. A
reset occurs on the falling edge of a high-to-low transition on the
RESET
pin. This initializes the pixel port such that the data on
the pixel inputs pins is ignored. See Appendix 8 for the register
settings after
RESET
is applied.
REAL-TIME CONTROL, SUBCARRIER RESET, AND
TIMING RESET
Together with the SCRESET/RTC/TR pin and of Mode
Register 4 (Genlock Control), the ADV7190/ADV7191 can
be used in (a) Timing Reset Mode, (b) Subcarrier Phase
Reset Mode or (c) RTC Mode.
(a) A TIMING RESET is achieved in holding this pin high. In
this state the horizontal and vertical counters will remain reset.
On releasing this pin (set to low), the internal counters will
commence counting again. The minimum time the pin has
to be held high is 37 ns (1 clock cycle at 27 MHz), otherwise
the reset signal might not be recognized.
(b) The SUBCARRIER PHASE will reset to that of Field 0 at
the start of the following field when a low-to-high transition
occurs on this input pin.
(c) In RTC MODE, the ADV7190/ADV7191 can be used to
lock to an external video source.
The real-time control mode allows the ADV7190/ADV7191
to automatically alter the subcarrier frequency to compen-
sate for line length variations. When the part is connected to
a device that outputs a digital datastream in the RTC format
such as an ADV7185 video decoder (see Figure 32), the part
will automatically change to the compensated subcarrier
frequency on a line-by-line basis. This digital datastream is
67 bits wide and the subcarrier is contained in Bits 0 to 21.
Each bit is two clock cycles long. 00Hex should be written
into all four Subcarrier Frequency registers when using this
mode. (Mode Register 4.)
SCH PHASE MODE
The SCH phase is configured in default mode to reset every
four (NTSC) or eight (PAL) fields to avoid an accumulation of
SCH phase error over time. In an ideal system, zero SCH phase
error would be maintained forever, but in reality, this is impos-
sible to achieve due to clock frequency variations. This effect is
reduced by the use of a 32-bit DDS, which generates this SCH.
Resetting the SCH phase every four or eight fields avoids the
accumulation of SCH phase error, and results in very minor SCH
phase jumps at the start of the four or eight field sequence.
Automatically resetting the SCH phase should not be done if
the video source does not have stable timing or the ADV7190/
ADV7191 is configured in RTC mode. Under these conditions
(unstable video) the Subcarrier Phase Reset should be en-
abled but no reset applied. In this configuration the SCH
Phase will never be reset; this means that the output video will
now track the unstable input video.
The Subcarrier Phase Reset, when applied, will reset the SCH
phase to Field 0 at the start of the next field (e.g., Subcarrier
Phase Reset applied in Field 5 (PAL) on the start of the next
field SCH phase will be reset to Field 0). (Mode Register 4.)
SLEEP MODE
If, after
RESET
, the SCRESET/RTC/TR and NTSC_PAL pins
are both set high, the ADV7190/ADV7191 will power-up in
Sleep Mode to facilitate low power consumption before all
registers have been initialized. If Power-Up in Sleep Mode is
disabled, Sleep Mode control passes to the Sleep Mode control
in Mode Register 2 (i.e., control via I
2
C). (Mode Register 2
and Mode Register 6.)
SQUARE PIXEL MODE
The ADV7190/ADV7191 can be used to operate in square pixel
mode. For NTSC operation an input clock of 24.5454 MHz is
required. Alternatively, for PAL operation, an input clock of
29.5 MHz is required. The internal timing logic adjusts ac-
cordingly for square pixel mode operation. Square pixel mode
is not available in 4
×
Oversampling mode. (Mode Register 2.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7191KST | Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs |
| ADV7190 | Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs |
| ADV7192KST | Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs |
| ADV7192 | Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs |
| ADV7194KST | Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7191KST | 制造商:Analog Devices 功能描述:Video Encoder 6DAC 10-Bit 64-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:54M 4X STD DEF ENCODER NON-MACRO I.C. - Tape and Reel |
| ADV7191KSTZ | 制造商:Analog Devices 功能描述:Video Encoder 6DAC 10-Bit 64-Pin LQFP 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
| ADV7192 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs |
| ADV7192KST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs |
| ADV7194 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling |
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