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參數資料
| 型號： | ADV7189KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Multiformat SDTV Video Decoder |
| 中文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | LEAD FREE, MS-026-BEC, LQFP-80 |
| 文件頁數： | 12/104頁 |
| 文件大小： | 890K |
| 代理商： | ADV7189KST |
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ADV7189
Pin No.
29
Rev. A | Page 12 of 104
Mnemonic
XTAL
Type
I
Function
This is the input pin for the 27 MHz crystal, or can be overdriven by an external 3.3 V, 27 MHz
clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
This pin should be connected to the 27 MHz crystal or left as a no connect if an external 3.3 V
27 MHz clock oscillator source is used to clock the ADV7189. In crystal mode, the crystal must
be a fundamental crystal.
A logic low on this pin places the ADV7189 in a power-down mode. Refer to the I
2
C Control
Register Map section for more options on power-down modes for the ADV7189.
When set to a logic low, OE enables the pixel output bus, P19–P0 of the ADV7189. A logic high
on the OE pin places Pins P19–P0, HS, VS, SFL/SYNC_OUT into a high impedance state.
The recommended external loop filter must be connected to this ELPF pin, as shown in
Figure 42.
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the
subcarrier frequency when this decoder is connected to any Analog Devices, Inc. digital video
encoder.
Internal Voltage Reference Output. Refer to Figure 42 for a recommended capacitor network
for this pin.
The CML pin is a common-mode level for the internal ADCs. Refer to Figure 42 for a
recommended capacitor network for this pin.
ADC’s Capacitor Network. Refer to Figure 42 for a recommended capacitor network for this pin.
ADC’s Capacitor Network. Refer to Figure 42 for a recommended capacitor network for this pin.
28
XTAL1
O
36
PWRDN
I
79
OE
I
37
ELPF
I
12
SFL
O
51
REFOUT
O
52
CML
O
48, 49
54, 55
CAPY1, CAPY2
CAPC1, CAPC2
I
I
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