參數(shù)資料
型號: ADV7189KST
廠商: ANALOG DEVICES INC
元件分類: 顏色信號轉換
英文描述: Multiformat SDTV Video Decoder
中文描述: COLOR SIGNAL DECODER, PQFP80
封裝: LEAD FREE, MS-026-BEC, LQFP-80
文件頁數(shù): 11/104頁
文件大?。?/td> 890K
代理商: ADV7189KST
ADV7189
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. A | Page 11 of 104
F
80
O
79
N
78
N
77
P
76
P
75
P
74
P
73
D
72
D
71
N
70
N
69
S
68
S
67
A
66
N
65
R
64
N
63
A
62
A
61
VS
HS
1
2
DGND
DVDDIO
3
4
P15
P14
P13
P12
5
6
7
8
DGND
DVDD
10
NC
11
SFL
12
NC
13
DGND
14
DVDDIO
15
NC
16
P11
17
P10
18
P9
19
P8
20
9
AIN5
AIN11
AIN4
AIN10
AGND
CAP C2
CAP C1
AGND
CML
REFOUT
AVDD
CAP Y2
CAP Y1
AGND
AIN3
AIN9
AIN2
AIN8
AIN1
AIN7
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P
21
P
22
P
23
P
24
N
25
L
26
L
27
X
28
X
29
D
30
D
31
P
32
P
33
P
34
P
35
P
36
E
37
P
38
A
39
A
40
ADV7189
TOP VIEW
(Not to Scale)
NC = NO CONNECT
0
Figure 5. 80-Lead LQFP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
3, 9, 14, 31, 71
DGND
39, 40, 47, 53,
56
4, 15
DVDDIO
10, 30, 72
DVDD
50
AVDD
38
PVDD
41–46, 57–62
AIN1–AIN12
11, 13, 16, 25,
63, 65, 69, 70,
77, 78
5–8, 17–24,
32–35, 73–76
2
HS
1
VS
80
FIELD
67
SDA
68
SCLK
66
ALSB
Type
G
G
Function
Digital Ground.
Analog Ground.
AGND
P
P
P
P
I
Digital I/O Supply Voltage (3.3 V).
Digital Core Supply Voltage (1.8 V).
Analog Supply Voltage (3.3 V).
PLL Supply Voltage (1.8 V).
Analog Video Input Channels.
No Connect Pins.
NC
P0–P19
O
Video Pixel Output Port.
O
O
O
I/O
I
I
HS is a horizontal synchronization output signal.
VS is a vertical synchronization output signal.
FIELD is a field synchronization output signal.
I
2
C Port Serial Data Input/Output Pin.
I
2
C Port Serial Clock Input (Max Clock Rate of 400 kHz).
This pin selects the I
2
C address for the ADV7189. ALSB set to a Logic 0 sets the address for a
write as 0x40; for ALSB set to a logic high, the address selected is 0x42.
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7189 circuitry.
This is a line-locked output clock for the pixel data output by the ADV7189. Nominally 27 MHz,
but varies up or down according to video line length.
This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the ADV7189.
Nominally 13.5 MHz, but varies up or down according to video line length.
64
RESET
I
27
LLC1
O
26
LLC2
O
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