參數(shù)資料
型號(hào)： ADV7185KST
廠商： ANALOG DEVICES INC
元件分類(lèi)： 顏色信號(hào)轉(zhuǎn)換
英文描述： Professional NTSC/PAL Video Decoder with 10-Bit CCIR656 Output
中文描述： COLOR SIGNAL DECODER, PQFP80
封裝： PLASTIC, LQFP-80
文件頁(yè)數(shù)： 17/41頁(yè)
文件大小： 730K
代理商： ADV7185KST
REV. 0
ADV7185
–17–
Control and Pixel Interface FIFO Modes
When the ADV7185 is configured to operate in this mode, pixel
data generated within the part is buffered by a 512-pixel deep FIFO.
Only active video pixels and control codes are written into the FIFO;
the others have been dropped. In this mode, the output is operating
asynchronously and a CLKIN must be provided to clock pixels out
of the FIFO. The CLKIN must operate faster than the effective
data
transfer rate into the FIFO. This rate will be determined by the
number of active pixels per line. If the CLKIN is not above this, the
FIFO may overflow. The ADV7185 controls the FIFO when set to
operate in SCAPI mode. DV (data valid) is internally fed back to
the RD (read enable), unlike the synchronous pixel mode where DV
will not indicate the validity of the current pixel and only acts as an
indication of how much data is stored in the FIFO. DV will go high
at the same time as AFF and remain high until the FIFO is empty.
By internally setting DV to RD, the system ensures that the
FIFO never overflows. When using this mode, the status of data
on the
pixel outputs can be determined by two indicators, DV and
QCLK.
DV will go active two clock cycles (LLC1) before valid data
appears
on the bus. QCLK is a qualified clock derived from
CLKIN, but
will only be present when valid pixel data is output
from the FIFO.
DV indicates valid pixel or control code data.
Using these two
control signals, the user can differentiate between
pixel information
and invalid data. Figure 25 shows the basic
timing
relationship for this mode.
The operation of the ADV7185 in CAPI mode is similar to that
of SCAPI mode with the exception that now the FIFO is con-
trolled by the system; the system must monitor the almost full
flag (AFF), the almost empty flag (AEF), and control the FIFO
read enable (RD). Unlike SCAPI mode, the QCLK is not gated
and is therefore continuous. Figure 26 shows the basic timing
relationship of this mode.
PIXEL DATA
DV
CLKIN
QCLK
AFF
AEF
NOTES
1. THE POLARITY OF AFF AND AEF ARE CONTROLLED BY THE PFF BIT.
2. DV POLARITY IS SET BY THE PDV BIT.
Figure 25. SCAPI Output Mode FIFO Operation
RD
CLKIN
QCLK
AFF
AEF
THE POLARITY OF AFF AND AEF ARE CONTROLLED BY THE PFF BIT.
DATA
Figure 26. CAPI Output Mode FIFO Operation
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7186 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Video Decoder and Display Processor
ADV7186BBCZ 功能描述:IC VIDEO DECODER 196CSPBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類(lèi)型:調(diào)諧器 應(yīng)用:移動(dòng)電話，手機(jī)，視頻顯示器 安裝類(lèi)型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱(chēng):SP000365064
ADV7186BBCZ-RL 功能描述:IC VIDEO DECODER 196CSPBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類(lèi)型:調(diào)諧器 應(yīng)用:移動(dòng)電話，手機(jī)，視頻顯示器 安裝類(lèi)型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱(chēng):SP000365064
ADV7186BBCZ-T 功能描述:IC VIDEO DECODER 196CSPBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類(lèi)型:調(diào)諧器 應(yīng)用:移動(dòng)電話，手機(jī)，視頻顯示器 安裝類(lèi)型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱(chēng):SP000365064
ADV7186BBCZ-TL 功能描述:IC VIDEO DECODER 196CSPBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類(lèi)型:調(diào)諧器 應(yīng)用:移動(dòng)電話，手機(jī)，視頻顯示器 安裝類(lèi)型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱(chēng):SP000365064
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