參數(shù)資料
型號(hào): ADV7183BBSTZ
廠商: ANALOG DEVICES INC
元件分類: 顏色信號(hào)轉(zhuǎn)換
英文描述: Multiformat SDTV Video Decoder
中文描述: COLOR SIGNAL DECODER, PQFP80
封裝: LEAD FREE, MS-026-BEC, LQFP-80
文件頁(yè)數(shù): 23/100頁(yè)
文件大?。?/td> 844K
代理商: ADV7183BBSTZ
ADV7183B
SRLS Select Raw Lock Signal, Address 0x51[6]
Using the SRLS bit, the user can choose between two sources for
determining the lock status (per Bits[1:0] in the Status 1 register).
Rev. B | Page 23 of 100
The time_win signal is based on a line-to-line evaluation of
the horizontal synchronization pulse of the incoming video.
It reacts quite quickly.
The free_run signal evaluates the properties of the
incoming video over several fields and takes vertical
synchronization information into account.
Setting SRLS to 0 (default) selects the free_run signal.
Setting SRLS to 1 selects the time_win signal.
FSCLE F
SC
Lock Enable, Address 0x51[7]
The FSCLE bit allows the user to choose whether the status of
the color subcarrier loop is taken into account when the overall
lock status is determined and presented via Bits[1:0] in Status
Register 1. This bit must be set to 0 when operating in YPrPb
component mode to generate a reliable HLOCK status bit.
Setting
FSCLE to 0 (default) makes the overall lock status
dependent on only horizontal sync lock.
Setting
FSCLE to 1 makes the overall lock status dependent on
horizontal sync lock and F
SC
lock.
VS_Coast[1:0] Address 0xF9[3:2]
These bits are used to set VS free-run (coast) frequency.
Table 19. VS_COAST[1:0] Function
VS_COAST[1:0]
Description
00 (default)
Auto coast mode—follows VS
frequency from last video input
01
Forces 50 Hz coast mode
10
Forces 60 Hz coast mode
11
Reserved
CIL[2:0] Count Into Lock, Address 0x51[2:0]
CIL[2:0] determines the number of consecutive lines for which
the lock condition must be true before the system switches into
the locked state, and reports this via Status 0[1:0]. It counts the
value in lines of video.
Table 20. CIL Function
CIL[2:0]
000
001
010
011
100 (default)
101
110
111
Description
1
2
5
10
100
500
1000
100000
COL[2:0] Count Out-of-Lock, Address 0x51[5:3]
COL[2:0] determines the number of consecutive lines for which
the out-of-lock condition must be true before the system switches
into unlocked state, and reports this via Status 0[1:0]. It counts
the value in lines of video.
Table 21. COL Function
COL[2:0]
000
001
010
011
100 (default)
101
110
111
COLOR CONTROLS
These registers allow the user to control the picture appearance,
including control of the active data in the event of video being
lost. These controls are independent of any other controls. For
instance, brightness control is independent from picture clamp-
ing, although both controls affect the signal’s dc level.
Description
1
2
5
10
100
500
1000
100000
CON[7:0] Contrast Adjust, Address 0x08[7:0]
This allows the user to adjust the contrast of the picture.
Table 22. CON Function
CON[7:0]
Description
0x80 (default)
Gain on luma channel = 1
0x00
Gain on luma channel = 0
0xFF
Gain on luma channel = 2
SD_SAT_Cb[7:0] SD Saturation Cb Channel,
Address 0xE3[7:0]
This register allows the user to control the gain of the Cb
channel only. The user can adjust the saturation of the picture.
Table 23. SD_SAT_Cb Function
SD_SAT_Cb[7:0]
Description
0x80 (default)
Gain on Cb channel = 0 dB
0x00
Gain on Cb channel = 42 dB
0xFF
Gain on Cb channel = +6 dB
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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