參數(shù)資料
型號(hào): ADV7183B
廠商: Analog Devices, Inc.
英文描述: Multiformat SDTV Video Decoder
中文描述: 標(biāo)清多格式視頻解碼器
文件頁(yè)數(shù): 82/100頁(yè)
文件大?。?/td> 844K
代理商: ADV7183B
ADV7183B
Rev. B | Page 82 of 100
Bits
4
0
0
1
1
0
0
1
1
Comments
1 line of video.
2 lines of video.
5 lines of video.
10 lines of video.
100 lines of video.
500 lines of video.
1000 lines of video.
100000 lines of video.
1 line of video.
2 lines of video.
5 lines of video.
10 lines of video.
100 lines of video.
500 lines of video.
1000 lines of video.
100000 lines of video.
Over field with vertical
info.
Line-to-line evaluation.
Lock status set only by
horizontal lock.
Lock status set by
horizontal lock and
subcarrier lock.
Set to default.
LLC1 (nominal 27 MHz)
selected out on LLC1 pin.
LLC2 (nominally
13.5 MHz) selected out on
LLC1 pin.
Set to default.
No WSS detected.
WSS detected.
No CCAP signals
detected.
CCAP sequence detected.
No EDTV sequence
detected.
EDTV sequence detected.
No CGMS transition
detected.
CGMS sequence
decoded.
Notes
Subaddress
0x51
Register
Lock
Count
Bit Description
CIL[2:0]. Count-into-lock determines
the number of lines the system must
remain in lock before showing a
locked status.
7
6
0
5
0
0
0
0
1
1
1
1
3
0
1
0
1
0
1
0
1
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
COL[2:0]. Count-out-of-lock
determines the number of lines the
system must remain out-of-lock
before showing a lost-locked status.
SRLS. Select raw lock signal. Selects
the determination of the lock status.
0
1
FSCLE. Fsc lock enable.
1
Reserved
LLC_PAD_SEL[2:0]. Enables manual
selection of clock for LLC1 pin.
0
0
0
0
0
0
0
1
0
1
For 16-bit 4:2:2 out,
OF_SEL[3:0] = 0010.
0x8F
Free Run
Line
Length 1
Reserved
WSSD. Screen signaling detected.
0
0
0
1
Read only status bits.
CCAPD. Closed caption data.
0
1
EDTVD. EDTV sequence.
0
1
CGMSD. CGMS sequence.
1
0x90
VBI Info
(Read Only)
Reserved.
x
x
x
x
x
x
x
x
x
x
x
x
0x91
WSS1
(Read Only)
WSS1[7:0]
Wide screen signaling data.
0x92
WSS2
(Read Only)
WSS2
(Read Only)
EDTV2
(Read Only)
WSS2[7:0]
Wide screen signaling data.
WSS2[7:0]
Wide screen signaling data.
EDTV2[7:0]
EDTV data register.
EDTV3[7:0]
EDTV data register.
CGMS1[7:0]
CGMS data register.
x
x
x
x
x
x
x
x
WSS2[7:6] are
undetermined.
0x93
x
x
x
x
x
x
x
x
0x94
x
x
x
x
x
x
x
x
0x95
EDTV3
(Read Only)
x
x
x
x
x
x
x
x
EDTV3[7:6] are
undetermined.
EDTV3[5] is reserved
for future use.
0x96
CGMS1
(Read Only)
x
x
x
x
x
x
x
x
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