參數(shù)資料
型號: ADV7183B
廠商: Analog Devices, Inc.
英文描述: Multiformat SDTV Video Decoder
中文描述: 標清多格式視頻解碼器
文件頁數(shù): 40/100頁
文件大?。?/td> 844K
代理商: ADV7183B
ADV7183B
VS and FIELD Configuration
The following controls allow the user to configure the behavior
of the VS and FIELD output pins and to generate embedded AV
codes:
ADV encoder-compatible signals via NEWAVMODE
Rev. B | Page 40 of 100
PVS, PF
HVSTIM
VSBHO, VSBHE
VSEHO, VSEHE
For NTSC control:
NVBEGDELO, NVBEGDELE, NVBEGSIGN,
NVBEG[4:0]
NVENDDELO, NVENDDELE, NVENDSIGN,
NVEND[4:0]
NFTOGDELO, NFTOGDELE, NFTOGSIGN,
NFTOG[4:0]
For PAL control:
PVBEGDELO, PVBEGDELE, PVBEGSIGN,
PVBEG[4:0]
PVENDDELO, PVENDDELE, PVENDSIGN,
PVEND[4:0]
PFTOGDELO, PFTOGDELE, PFTOGSIGN,
PFTOG[4:0]
NEWAVMODE New AV Mode, Address 0x31[4]
When NEWAVMODE is 0, EAV/SAV codes are generated to
suit ADI encoders. No adjustments are possible.
Setting NEWAVMODE to 1 (default) enables the manual posi-tion
of the Vsync, Field, and AV codes using Register 0x34 to Register
0x37 and Register 0xE5 to Register 0xEA. Default register settings
are CCIR656-compliant; see
211H
Figure 21 for NTSC and
212H
Figure 26 for
PAL. For recommended manual user settings, see
213H
Table 56 and
214H
Figure 22 for NTSC; see
215H
Table 57 and
216H
Figure 27 for PAL.
HVSTIM Horizontal VS Timing, Address 0x31[3]
The HVSTIM bit allows the user to select where the VS signal is
being asserted within a line of video. Some interface circuitry
can require VS to go low while HS is low.
When HVSTIM is 0 (default), the start of the line is relative
to HSE.
When HVSTIM is 1, the start of the line is relative to HSB.
VSBHO VS Begin Horizontal Position Odd,
Address 0x32[7]
The VSBHO and VSBHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to change state only
when HS is high/low.
When VSBHO is 0 (default), the VS pin goes high at the middle
of a line of video (odd field).
When VSBHO is 1, the VS pin changes state at the start of a line
(odd field).
VSBHE VS Begin Horizontal Position Even,
Address 0x32[6]
The VSBHO and VSBHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to change state when
only HS is high/low.
When VSBHE is 0, the VS pin goes high at the middle of a line
of video (even field).
When VSBHE is 1 (default), the VS pin changes state at the start
of a line (even field).
VSEHO VS End Horizontal Position Odd,
Address 0x33[7]
The VSEHO and VSEHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to change state only
when HS is high/low.
When VSEHO is 0 (default), the VS pin goes low (inactive) at
the middle of a line of video (odd field).
When VSEHO is 1, the VS pin changes state at the start of a line
(odd field).
VSEHE VS End Horizontal Position Even,
Address 0x33[6]
The VSEHO and VSEHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to change state only
when HS is high/low.
When VSEHE is 0 (default), the VS pin goes low (inactive) at
the middle of a line of video (even field).
When VSEHE is 1, the VS pin changes state at the start of a line
(even field).
PVS Polarity VS, Address 0x37[5]
The polarity of the VS pin can be inverted using the PVS bit.
When PVS is 0 (default), VS is active high.
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