參數(shù)資料
型號： ADV7177KSZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 5/44頁
文件大?。?/td> 0K
描述： IC DAC VIDEO NTSC 3-CH 44MQFP
產(chǎn)品變化通告： ADV7xxx Obsolescence 16/Jan/2012
標(biāo)準(zhǔn)包裝： 800
類型： 視頻編碼器
應(yīng)用： 機頂盒，電視
電壓 - 電源，模擬： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 44-QFP
供應(yīng)商設(shè)備封裝： 44-MQFP（10x10）
包裝： 帶卷 (TR)
ADV7177/ADV7178
Rev. C | Page 13 of 44
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
44
CLOCK
43
CLOCK
42
GND
41
P4
40
P3
39
P2
38
P1
37
P0
36
OSD_2
35
OSD_1
34
OSD_0
32
VREF
31
DAC A
30
VAA
27
DAC B
28
VAA
29
GND
33
RSET
26
DAC C
25
COMP
24
SDATA
23
SCLOCK
2
CLOCK/2
3
P5
4
P6
7
P9
6
P8
5
P7
1
VAA
8
P10
9
P11
10
P12
11
OSD_EN
12
P13
13
P14
14
P15
15
H
SYN
C
16
FIELD
/VSYN
C
17
BLANK
18
ALS
B
19
GND
20
V
AA
21
GND
22
R
ESET
PIN 1
AD7177/ADV7178
MQFP
TOP VIEW
(Not to Scale)
00228-006
Figure 6. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
I/O
Function
1, 20, 28, 30
VAA
P
Power Supply.
2
CLOCK/2
O
Synchronous Clock Output Signal. Can be either 27 MHz or 13.5 MHz; this can be controlled by MR32
and MR33 in Mode Register 3.
3 to 10,
12 to 14,
37 to 41
P5 to P12,
P13 to 14,
P0 to P4
I
8-Bit, 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or 16-Bit YCrCb Pixel Port (P15–P0). P0 represents the
LSB.
11
OSD_EN
I
Enables OSD input data on the video outputs.
15
HSYNC
I/O
HSYNC (Modes 1 and 2) Control Signal. This pin can be configured to output (master mode) or accept
(slave mode) Sync signals.
16
FIELD/
VSYNC
I/O
Dual Function Field (Mode 1) and VSYNC (Mode 2) Control Signal. This pin can be configured to
output (master mode) or accept (slave mode) these control signals.
17
BLANK
I/O
Video Blanking Control Signal. The pixel inputs are ignored when this is Logic 0. This signal is optional.
18
ALSB
I
TTL Address Input. This signal sets up the LSB of the MPU address.
19, 21, 29, 42
GND
G
Ground Pin.
22
RESET
I
The input resets the on-chip timing generator and sets the ADV7177/ADV7178 into default mode. This
is NTSC operation, Timing Slave Mode 0, 8-bit operation, 2× composite and S VHS out.
23
SCLOCK
I
MPU Port Serial Interface Clock Input.
24
SDATA
I/O
MPU Port Serial Data Input/Output.
25
COMP
O
Compensation Pin. Connect a 0.1 F capacitor from COMP to VAA.
26
DAC C
O
DAC C Analog Output.
27
DAC B
O
DAC B Analog Output.
31
DAC A
O
DAC A Analog Output.
32
VREF
I/O
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
33
RSET
I
A 300 resistor connected from this pin to GND is used to control full-scale amplitudes of the video
signals.
34–36
OSD_0 to
OSD_2
I
On Screen Display Inputs.
43
CLOCK
O
Crystal Oscillator Output (to crystal). Leave unconnected if no crystal is used.
44
CLOCK
I
Crystal Oscillator Input. If no crystal is used, this pin can be driven by an external TTL clock source; it
requires a stable 27 MHz reference clock for standard operation. Alternatively, a 24.5454 MHz (NTSC)
or 29.5 MHz (PAL) can be used for square pixel operation.
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