參數(shù)資料
型號(hào)： ADV7177KSZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/44頁(yè)
文件大小： 0K
描述： IC DAC VIDEO NTSC 3-CH 44MQFP
產(chǎn)品變化通告： ADV7xxx Obsolescence 16/Jan/2012
標(biāo)準(zhǔn)包裝： 800
類型： 視頻編碼器
應(yīng)用： 機(jī)頂盒，電視
電壓 - 電源，模擬： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 44-QFP
供應(yīng)商設(shè)備封裝： 44-MQFP（10x10）
包裝： 帶卷 (TR)
ADV7177/ADV7178
Rev. C | Page 26 of 44
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of
sequence with normal read and write operations, they cause an
immediate jump to the idle condition. During a given SCLOCK
high period, the user should issue only one start condition, one
stop condition, or a single stop condition followed by a single
start condition. If an invalid subaddress is issued by the user,
the devices do not issue an acknowledge and return to the idle
condition. If, in auto-increment mode, the user exceeds the
highest subaddress, the following actions are taken.
In read mode, the highest subaddress register contents continue
to be output until the master device issues a no acknowledge.
This indicates the end of a read. A no-acknowledge condition is
where the SDATA line is not pulled low on the ninth pulse.
In write mode, the data for the invalid byte is not loaded into
any subaddress register, a no acknowledge is issued by the
ADV7177/ADV7178, and the parts return to the idle condition.
Figure 29 illustrates an example of data transfer for a read
sequence and the start and stop conditions. Figure 30 shows
bus write and read sequences.
1–7
8
9
1–7
8
9
1–7
8
9
P
S
START ADDR R/W
ACK
SUBADDRESS ACK
DATA
ACK
STOP
SDATA
SCLOCK
00228-029
Figure 29. Bus Data Transfer
DATA
A(S)
S
SLAVE ADDR A(S)
SUB ADDR
A(S)
LSB = 0
LSB = 1
DATA
A(S) P
S
SLAVE ADDR A(S)
SUB ADDR
A(S) S
SLAVE ADDR
A(S)
DATA
A(M)
DATA
P
WRITE
SEQUENCE
READ
SEQUENCE
A(S) = NO ACKNOWLEDGE BY SLAVE
A(M) = NO ACKNOWLEDGE BY MASTER
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S = START BIT
P = STOP BIT
00228-030
Figure 30. Write and Read Sequences
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