參數(shù)資料
型號: ADV7172KST
廠商: ANALOG DEVICES INC
元件分類: 顏色信號轉(zhuǎn)換
英文描述: Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management
中文描述: COLOR SIGNAL ENCODER, PQFP48
封裝: PLASTIC, TQFP-48
文件頁數(shù): 37/59頁
文件大?。?/td> 455K
代理商: ADV7172KST
ADV7172/ADV7173
–37–
REV. A
TELETEXT CONTROL REGISTER TC07 (TC07–TC00)
(ADDRESS (SR4–SR0) = 1CH)
Teletext Control Register is an 8-bit-wide register. See Figure
59.
TTXREQ Rising Edge Control (TC07–TC04)
These bits control the position of the rising edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles.
TTXREQ Falling Edge Control (TC03–TC00)
These bits control the position of the falling edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles. This controls the active window for Teletext
data. Increasing this value reduces the amount of Teletext Bits
below the default of 360. If Bits TC03–TC00 are 00Hex when
Bits TC07–TC04 are changed, then the falling edge of TTREQ
will track that of the rising edge (i.e., the time between the
falling and rising edge remains constant).
CGMS_WSS REGISTER 0 C/W0 (C/W07–C/W00)
(ADDRESS (SR4–SR0) = 19H)
CGMS_WSS Register 0 is an 8-bit-wide register. Figure 60
shows the operations under control of this register.
TC01
TC00
TC07
TC02
TC04
TC03
TC05
TC06
TTXREQ RISING EDGE CONTROL
TC07 TC06
TC05 TC04
0
0
"
1
1
0
0
"
1
1
0
0
"
1
1
0
1
"
0
1
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
TTXREQ FALLING EDGE CONTROL
TC03 TC02
TC01 TC00
0
0
"
1
1
0
0
"
1
1
0
0
"
1
1
0
1
"
0
1
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
Figure 59. Teletext Control Register
CGMS CRC CHECK
CONTROL
C/W04
0
1
DISABLE
ENABLE
WIDE SCREEN SIGNAL
CONTROL
C/W07
0
1
DISABLE
ENABLE
C/W07
C/W06
C/W05
C/W04
C/W03
C/W02
C/W01
C/W00
CGMS ODD FIELD
CONTROL
C/W05
0
1
DISABLE
ENABLE
C/W03–C/W00
CGMS DATA BITS
CGMS EVEN FIELD
CONTROL
C/W06
0
1
DISABLE
ENABLE
Figure 60. CGMS_WSS Register 0
C/W BIT DESCRIPTION
CGMS Data Bits (C/W03–C/W00)
These four data bits are the final four bits of CGMS data output
stream. Note it is CGMS data ONLY in these bit positions i.e.,
WSS data does not share this location.
CGMS CRC Check Control (C/W04)
When this bit is enabled (“1”), the last six bits of the CGMS
data, i.e., the CRC check sequence, are calculated internally by
the ADV7172/ADV7173. If this bit is disabled (“0”), the CRC
values in the register are output to the CGMS data stream.
CGMS Odd Field Control (C/W05)
When this bit is set (“1”), CGMS is enabled for odd fields.
Note that this is only valid in NTSC mode.
CGMS Even Field Control (C/W06)
When this bit is set (“1”), CGMS is enabled for even fields.
Note that this is only valid in NTSC mode.
WSS Control (C/W07)
When this bit is set (“1”), wide screen signalling is enabled.
Note that this is only valid in PAL mode.
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參數(shù)描述
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ADV7173 制造商:AD 制造商全稱:Analog Devices 功能描述:Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management