參數(shù)資料
型號(hào)： ADV7172KST
廠商： ANALOG DEVICES INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management
中文描述： COLOR SIGNAL ENCODER, PQFP48
封裝： PLASTIC, TQFP-48
文件頁(yè)數(shù)： 25/59頁(yè)
文件大?。?/td> 455K
代理商： ADV7172KST
ADV7172/ADV7173
–25–
REV. A
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0
1
WRITE
READ
0
1
0
1
0
1
A1
X
Figure 40. ADV7173 Slave Address
To control the various devices on the bus the following protocol
must be followed. First the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDATA while SCLOCK remains high. This indicates that
an address/data stream will follow. All peripherals respond to
the Start condition and shift the next eight bits (7-bit address +
R/
W
bit). The bits are transferred from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDATA and SCLOCK
lines waiting for the Start condition and the correct transmitted
address. The R/
W
bit determines the direction of the data. A
Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the LSB
of the first byte means that the master will read information
from the peripheral.
The ADV7172/ADV7173 acts as a standard slave device on the
bus. The data on the SDATA pin is eight bits long, supporting
the 7-bit addresses plus the R/
W
bit. It interprets the first byte
as the device address and the second byte as the starting sub-
address. The subaddresses auto increment allows data to be
written to or read from the starting subaddress. A data transfer
is always terminated by a stop condition. The user can also
access any unique subaddress register on a one-by-one basis
without having to update all the registers. There is one excep-
tion. The subcarrier frequency registers should be updated in
sequence, starting with Subcarrier Frequency Register 0. The
auto increment function should then be used to increment and
access Subcarrier Frequency Registers 1, 2 and 3. The subcarrier
frequency registers should not be accessed independently.
Stop and Start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, then these cause an
immediate jump to the idle condition. During a given SCLOCK
high period the user should only issue one start condition, one
stop condition or a single stop condition followed by a single
start condition. If an invalid subaddress is issued by the user,
the ADV7172/ADV7173 will not issue an acknowledge and will
return to the idle condition. If, in autoincrement mode, the user
exceeds the highest subaddress the following action will be
taken:
1. In Read Mode the highest subaddress register contents will
continue to be output until the master device issues a no-
acknowledge. This indicates the end of a read. A no-
acknowledge condition is where the SDATA line is not
pulled low on the ninth pulse.
2. In Write Mode, the data for the invalid byte will not be loaded
into any subaddress register, a no-acknowledge will be issued
by the ADV7172/ADV7173 and the part will return to the
idle condition.
Figure 41 illustrates an example of data transfer for a read
sequence and the Start and Stop conditions.
1-7
8
9
1-7
8
9
1-7
8
9
P
S
START ADDR R/
W
ACK SUBADDRESS ACK
DATA
ACK
STOP
SDATA
SCLOCK
Figure 41. Bus Data Transfer
Figure 42 shows bus write and read sequences.
REGISTER ACCESSES
The MPU can write to or read from all of the registers of the
ADV7172/ADV7173 except the Subaddress Register, which is a
write-only register. The Subaddress Register determines which
register the next read or write operation accesses. All communi-
cations with the part through the bus start with an access to the
Subaddress Register. A read/write operation is then performed
from/to the target address, which then increments to the next
address until a Stop command on the bus is performed.
REGISTER PROGRAMMING
The following section describes each register, including subaddress
register, mode registers, subcarrier frequency registers, subcar-
rier phase register, timing registers, closed captioning extended
data registers, closed captioning data registers, NTSC pedestal
Control/PAL teletext control registers, CGMS/WSS registers,
contrast register, U- or V-scale registers, hue adjust register,
brightness control register and sharpness response register in
terms of its configuration. All registers can be read from as well
as written to.
DATA
A(S)
S
SLAVE ADDR A(S)
SUB ADDR
A(S)
LSB = 0
LSB = 1
DATA
A
(S) P
S
SLAVE ADDR
A(S)
SUB ADDR
A(S) S
SLAVE ADDR
A(S)
DATA
A
(M)
DATA
P
WRITE
SEQUENCE
READ
SEQUENCE
A
(S) = NO-ACKNOWLEDGE BY SLAVE
A
(M) = NO-ACKNOWLEDGE BY MASTER
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S = START BIT
P = STOP BIT
A(M)
Figure 42. Write and Read Sequences
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7172KST-REEL 制造商:Analog Devices 功能描述:
ADV7172KSTZ 制造商:Analog Devices 功能描述:
ADV7172KSTZ-REEL 功能描述:IC DAC VIDEO NTSC 6-CH 48-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799
ADV7173 制造商:AD 制造商全稱:Analog Devices 功能描述:Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management
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