參數(shù)資料
型號： ADV7150
廠商： Analog Devices, Inc.
英文描述： CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC(三通道,10位視頻RAM-D/A轉(zhuǎn)換器)
中文描述： 220兆赫的CMOS真彩色圖形三路10位顯存，數(shù)模轉(zhuǎn)換器（三通道，10位視頻RAM的的D / A轉(zhuǎn)換器）
文件頁數(shù)： 30/36頁
文件大小： 434K
代理商： ADV7150
ADV7150
–30–
REV. A
ADV7150 Initialization
After power has been supplied, the ADV7150 must be initial-
ized. T he Mode Register and Control Registers must be set.
T he values written to the various registers will be determined by
the desired operating mode of the part, i.e., T rue Color/Pseudo
Color, 2:1 Muxing/2:1 Muxing, etc.
T he following section gives examples of initialization of the
ADV7150 operating in various modes.
E xample 1
Color Mode
Multiplexing
Databus
RAM-DAC Resolution
SYNC
Pedestal
Register Initialization
Write
09H to Mode Register (MR1)
Write
08H to Mode Register (MR1)
Write
09H to Mode Register (MR1)
Write
29H to Mode Register (MR1)
Write
09H to Mode Register (MR1)
Write
04H to Address Register (A7–A0)
Write
FFH to Pixel Mask Register
Write
05H to Address Register (A7–A0)
Write
00H to Command Reg 1 (CR1)
Write
06H to Address Register (A7–A0)
Write
ECH to Command Reg 2 (CR2)
Write
07H to Address Register (A7–A0)
Write
C0H to Command Reg 3 (CR3)
24-Bit True Color
2:1
8-Bit
8-Bit
Enabled on IOG
7.5 IRE
C1
1
1
1
1
1
0
1
0
1
0
1
0
1
C0
1
1
1
1
1
0
0
0
0
0
0
0
0
R/
W
0
0
0
0
0
0
0
0
0
0
0
0
0
Comment
Resets to Normal Operation, 8-Bit Bus/RAM-DAC
*(Initializes Pipelining
*( “
*(Calibrates LOADOUT /LOADIN T iming
*( “
Address Reg Points to Pixel Mask Register
Sets the Pixel Mask to All “1s”
Address Reg Points to Command Register 1 (CR1)
Address Reg Points to Command Register 2 (CR2)
Sets 24-Bit Color, 7.5 IRE,
SYNC
on Green (IOG)
Address Reg Points to Command Register 3 (CR3)
Sets 2:1 Multiplexing, PRGCK OUT = CLOCK /4
Color Palette RAM Initialization
Write
00H to Address Register (A7–A0)
Write
00H (Red Data) to RAM Location (00H)
Write
00H (Green Data) to RAM Location (00H)
Write
00H (Blue Data) to RAM Location (00H)
Write
01H (Red Data) to RAM Location (01H)
Write
01H (Green Data) to RAM Location (01H)
Write
01H (Blue Data) to RAM Location (01H)
Write
FFH (Red Data) to RAM Location (FFH)
Write
FFH (Green Data) to RAM Location (FFH)
Write
FFH (Blue Data) to RAM Location (FFH)
C1
0
0
0
0
0
0
0
0
0
0
C0
0
1
1
1
1
1
1
1
1
1
R/
W
0
0
0
0
0
0
0
0
0
0
Comment
Points to Color Palette RAM
(Initializes Palette RAM
(
to a Linear Ramp**
(
(
(
(
(
(
(
(
(RAM Initialization Complete
*
*T hese four command lines reset the ADV7150. T he pipelines for each of the Red, Creen and Blue pixel inputs are synchronously reset to the Multiplexer’s
“A” input. Mode Register bit MR10 is written by a “1” followed by “0” followed by “1.” LOADIN/LOADOUT timing is internally synchronized by writing a “0”
followed by a “1” followed by a “0” to Mode Register MR15.
**T his sequence of instructions would, of course, normally be coded using some form of loop instruction.
APPE NDIX 5
INIT IALIZAT ION AND PROGRAMMING
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