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ADV7150
–14–
REV. A
CLOCK ,
CLOCK
Inputs
T he Clock Control Circuit is driven by the pixel clock inputs,
CLOCK and
CLOCK
. T hese inputs can be driven by a differ-
ential ECL oscillator running from a +5 V supply.
Alternatively, the ADV7150 CLOCK inputs can be driven by a
Programmable Clock Generator (Figure 15), such as the
ICS1562. T he ICS1562 is a monolithic, phase-locked-loop,
clock generator chip. It is capable of synthesizing differential
ECL output frequencies in a range up to 220 MHz from a single
low frequency reference crystal.
V
CC
GND
220
330
GND
+5V
CLOCK
CLOCK
CLOCK
GENERATOR
+5V
GND
V
AA
V
CLOCK
ADV7150
GND
D0-D3
CS R/W
ECL
OUT+
ECL
OUT–
V
REF
OUT
V
REF
V
AA
0.1
μ
F
LOW FREQUENCY
OSCILLATOR
V
CC
GND
220
330
Figure 15. PLL Clock Generator Driving CLOCK,
CLOCK
of
the ADV7150
CLOCK CONT ROL SIGNALS
LOADOUT
T he ADV7150 generates a LOADOUT control signal that runs
at a divided down frequency of the pixel CLOCK . T he frequency
is automatically set to the programmed multiplex rate, controlled
by CR37 and CR36 of Command Register 3.
f
LOADOUT
= f
CLOCK
/4
4:1 Multiplex Mode
f
LOADOUT
= f
CLOCK
/2
2:1 Multiplex Mode
f
LOADOUT
= f
CLOCK
1:1 Multiplex Mode
T he LOADOUT signal is used to directly drive the LOADIN
pixel latch signal of the ADV7150. T his is most simply achieved
by tying the LOADOUT and LOADIN pins together. Alterna-
tively, the LOADOUT signal can be used to drive the frame
buffer’s shift clock signals, returning to the LOADIN input de-
layed with respect to LOADOUT .
If it is not necessary to have a known fixed number of pipeline
delays, there is no limitation on the delay between LOAD-
OUT and LOADIN (LOADOUT [1] and LOADOUT [2]).
LOADIN and Pixel Data must conform to the setup and hold
times (t
8
and t
9
).
If, however, it is required that the ADV7150 has a fixed number
of pipeline delays (t
PD
), LOADOUT and LOADIN must con-
form to timing specifications t
10
and
τ
-t
11
as illustrated in Fig-
ures 4 to 7.
LOADOUT
LOADIN
PIXEL
DATA
ADV7150
VIDEO
FRAME
BUFFER
LOADOUT
LOADIN
ADV7150
VIDEO
FRAME
BUFFER
LOADOUT(1)
LOADOUT(2)
PIXEL
DATA
LOADIN
LOADOUT
LOADOUT(1)
LOADOUT(2)
DELAY
Figure 16. LOADOUT vs. Pixel Clock Input (CLOCK,
CLOCK
)
PRGC K OUT
T he PRGCK OUT control signal outputs a user programmable
clock frequency. It is a divided down frequency of the pixel
CLOCK
(see Figure 8). T he rising edge of PRGCK OUT is
synchronous to the rising edge of LOADOUT
f
PRGCKOUT
= f
CLOCK
/N
where
N
= 4, 8, 16 or 32.
One application of the PRGCK OUT is to use it as the master
clock frequency of the graphics subsystems processor or
controller.
SCK IN, SCK OUT
T hese video memory signals are used to minimize external sup-
port chips. Figure 17 illustrates the function that is provided.
An input signal applied to SCK IN is synchronously AND-ed
with the video blanking signal (
BLANK
). T he resulting signal is
output on SCK OUT . Figure 9 of the T iming Waveform section
shows the relationship between SCK OUT , SCK IN and
BLANK
.
SCKOUT
SCKIN
BLANK
LATCH
ENABLE
SYNC
Figure 17. SCKOUT Generation Circuit
T he SCK OUT signal is essentially the video memory shift con-
trol signal. It is stopped during the screen retrace. Figure 18
shows a suggested frame buffer to ADV7150 interface. T his is a
minimum chip solution and allows the ADV7150 control the
overall graphics system clocking and synchronization.
LOADOUT
LOADIN
SCKIN
SCKOUT
ADV7150
VIDEO
FRAME
BUFFER
PIXEL
DATA
BLANK
Figure 18. ADV7150 Interface Using SCKIN and SCKOUT