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| 型號： | ADuC848 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| 中文描述： | MicroConverter的多通道ADC的24-/16-Bit與嵌入式62 kB閃存以及單周期控制器 |
| 文件頁數(shù)： | 58/108頁 |
| 文件大?。?/td> | 1109K |
| 代理商： | ADUC848 |
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ADuC845/ADuC847/ADuC848
Mode 3 (Twin 16-Bit PWM)
In Mode 3, the PWM counter is fixed to count from 0 to 65536,
giving a fixed 16-bit PWM. Operating from the 12.58 MHz core
clock results in a PWM output rate of 192 Hz. The duty cycle of
the PWM outputs at P2.5 and P2.6 are independently
programmable.
Rev. A | Page 58 of 108
As shown in Figure 41, while the PWM counter is less than
PWM0H/L, the output of PWM0 (P2.5) is high. Once the PWM
counter equals PWM0H/L, PWM0 (P2.5) goes low and remains
low until the PWM counter rolls over.
Similarly, while the PWM counter is less than PWM1H/L, the
output of PWM1 (P2.6) is high. Once the PWM counter equals
PWM1H/L, PWM1 (P2.6) goes low and remains low until the
PWM counter rolls over.
In this mode, both PWM outputs are synchronized, that is, once
the PWM counter rolls over to 0, both PWM0 (P2.5) and PWM1
(P2.6) go high.
P2.6
P2.5
PWM COUNTER
PWM1H/L
0
65536
PWM0H/L
0
Figure 41. PWM Mode 3
Mode 4 (Dual NRZ 16-Bit Σ-
DAC)
Mode 4 provides a high speed PWM output similar to that of a
Σ-
DAC. Typically, this mode is used with the PWM clock
equal to 12.58 MHz.
In this mode, P1.0 and P1.1 are updated every PWM clock
(80 ns in the case of 12.58 MHz). Over any 65536 cycles (16-bit
PWM), PWM0 (P1.0) is high for PWM0H/L cycles and low for
(65536 – PWM0H/L) cycles. Similarly, PWM1 (P1.1) is high for
PWM1H/L cycles and low for (65536 – PWM1H/L) cycles.
If PWM1H is set to 4010H (slightly above one-quarter of FS),
typically P1.1 is low for three clocks and high for one clock
(each clock is approximately 80 ns). Over every 65536 clocks,
the PWM compromises for the fact that the output should be
slightly above one-quarter of full scale, by having a high cycle
followed by only two low cycles.
12.583MHz
16-BIT
80
μ
s
0
16-BIT
16-BIT
16-BIT
16-BIT
16-BIT
CARRY OUT AT P2.5
CARRY OUT AT P2.6
PWM0H/L = C000H
PWM1H/L = 4000H
0
1
0
0
LATCH
0
1
1
1
1
1
0
0
80
μ
s
Figure 42. PWM Mode 4
For faster DAC outputs (at lower resolution), write 0s to the
LSBs that are not required with a 1 in the LSB position. If, for
example, only 12-bit performance is required, write 0001 to the
4 LSBs. This means that a 12-bit accurate Σ -Δ DAC output can
occur at 3 kHz. Similarly, writing 00000001 to the 8 LSBs gives
an 8-bit accurate Σ-Δ DAC output at 49 kHz.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADUC848BCP62-3 | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| ADUC848BCP62-5 | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| ADUC848BCP8-3 | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| ADUC848BCP8-5 | Cable Gland (Clamp); Connector Shell Size:10SL, 12S; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Thread Size:5/8-24; Approval Categories:MIL-C-5015; Series:97 RoHS Compliant: No |
| ADUC848BS32-3 | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADUC848BCP32-3 | 制造商:Analog Devices 功能描述:10 CHANNEL 16 BIT ADC + FLASH 8 BIT UP - Trays |
| ADUC848BCP32-5 | 制造商:Analog Devices 功能描述:10 CHANNEL 16 BIT ADC + FLASH 8 BIT UP - Trays |
| ADUC848BCP62-3 | 制造商:Analog Devices 功能描述:MCU 8-Bit ADuC8xx 8052 CISC 62KB Flash 3.3V/5V 56-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:8BIT CISC 62KB FLASH 12.85MHZ 3.3V 56LFCSP - Bulk |
| ADUC848BCP62-5 | 制造商:Analog Devices 功能描述:MCU 8-bit ADuC8xx 8052 CISC 62KB Flash 3.3V/5V 56-Pin LFCSP EP |
| ADUC848BCP8-3 | 制造商:Analog Devices 功能描述:MCU 8-bit ADuC8xx 8052 CISC 62KB Flash 3.3V/5V 56-Pin LFCSP EP 制造商:Analog Devices 功能描述:10 CHANNEL 16 BIT ADC + FLASH 8 BIT UP - Trays 制造商:Rochester Electronics LLC 功能描述:10 CHANNEL 16 BIT ADC + FLASH 8 BIT UP - Bulk |
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