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參數(shù)資料
| 型號： | ADUC847BCPZ8-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 94/108頁 |
| 文件大小： | 0K |
| 描述： | IC MCU FLASH W/24BIT ADC 56-CSP |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.75 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x24b; D/A 1x12b，2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 包裝： | 托盤 |
| 配用： | EVAL-ADUC847QSZ-ND - KIT DEV QUICK START FOR ADUC847 |
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ADuC845/ADuC847/ADuC848
Data Sheet
Rev. C | Page 86 of 108
IEIP2—Secondary Interrupt Enable Register
SFR Address:
A9H
Power-On Default:
A0H
Bit Addressable:
No
Table 60. IEIP2 Bit Designations
Bit No.
Name
Description
7
----
Not Implemented. Write Don’t Care.
6
PTI
Time Interval Counter Interrupt Priority Setting (1 = High, 0 = Low).
5
PPSM
Power Supply Monitor Interrupt Priority Setting (1 = High, 0 = Low).
4
PSI
SPI/I2C Interrupt Priority Setting (1 = High, 0 = Low).
3
----
This bit must contain 0.
2
ETI
Set by the user to enable the time interval counter interrupt.
Cleared by the user to disable the time interval counter interrupt.
1
EPSMI
Set by the user to enable the power supply monitor interrupt.
Cleared by the user to disable the power supply monitor interrupt.
0
ESI
Set by the user to enable the SPI/I2C serial port interrupt.
Cleared by the user to disable the SPI/I2C serial port interrupt.
INTERRUPT PRIORITY
The interrupt enable registers are written by the user to enable
individual interrupt sources; the interrupt priority registers
allow the user to select one of two priority levels for each
interrupt. A high priority interrupt can interrupt the service
routine of a low priority interrupt, and if two interrupts of
different priorities occur at the same time, the higher level
interrupt is serviced first. An interrupt cannot be interrupted by
another interrupt of the same priority level. If two interrupts of
the same priority level occur simultaneously, the polling
sequence, as shown in Table 61, is observed.
Table 61. Priority within Interrupt Level
INTERRUPT VECTORS
When an interrupt occurs, the program counter is pushed onto
the stack, and the corresponding interrupt vector address is
loaded into the program counter. The interrupt vector addresses
are shown in Table 62.
Table 62. Interrupt Vector Addresses
Source
Vector Address
IE0
0003H
TF0
000BH
IE1
0013H
TF1
001BH
RI + TI
0023H
TF2 + EXF2
002BH
RDY0/RDY1 (ADuC845 only)
0033H
ISPI/I2CI
003BH
PSMI
0043H
TII
0053H
WDS
005BH
Source
Priority
Description
PSMI
1 (Highest)
Power Supply Monitor Interrupt
WDS
2
Watchdog Timer Interrupt
IE0
2
External Interrupt 0
RDY0/RDY1
3
ADC Interrupt
TF0
4
Timer/Counter 0 Interrupt
IE1
5
External Interrupt 1
TF1
6
Timer/Counter 1 Interrupt
ISPI/I2CI
7
SPI/I2C Interrupt
RI/TI
8
UART Serial Port Interrupt
TF2/EXF2
9
Timer/Counter 2 Interrupt
TII
11 (Lowest)
Timer Interval Counter Interrupt
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