參數(shù)資料
型號(hào)： ADUC847BCPZ8-5
廠商： Analog Devices Inc
文件頁數(shù)： 27/108頁
文件大小： 0K
描述： IC MCU FLASH W/24BIT ADC 56-CSP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大小： 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x24b; D/A 1x12b，2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
包裝： 托盤
配用： EVAL-ADUC847QSZ-ND - KIT DEV QUICK START FOR ADUC847
Data Sheet
ADuC845/ADuC847/ADuC848
Rev. C | Page 25 of 108
Power Control Register (PCON)
The PCON SFR contains bits for power-saving options and
general-purpose status flags as listed in Table 6.
SFR Address:
87H
Power-On Default:
00H
Bit Addressable:
No
Table 6. PCON SFR Bit Designations
Bit No.
Name
Description
7
SMOD
Double UART Baud Rate.
0 = Normal, 1 = Double Baud Rate.
6
SERIPD
Serial Power-Down Interrupt Enable. If this
bit is set, a serial interrupt from either SPI
or I2C can terminate the power-down
mode.
5
INT0PD
INT0 Power-Down Interrupt Enable.
If this bit is set, either a level (IT0 = 0) or a
negative-going transition (IT0 = 1) on the
INT0 pin terminates power-down mode.
4
ALEOFF
If set to 1, the ALE output is disabled.
3
GF1
General-Purpose Flag Bit.
2
GF0
General-Purpose Flag Bit.
1
PD
Power-Down Mode Enable. If set to 1, the
part enters power-down mode.
0
-----
Not Implemented. Write Don’t Care.
ADuC845/ADuC847/ADuC848 Configuration Register
(CFG845/CFG847/CFG848)
The CFG845/CFG847/CFG848 SFR contains the bits necessary
to configure the internal XRAM and the extended SP. By default,
it configures the user into 8051 mode, that is, extended SP, and
the internal XRAM are disabled. When using in a program, use
the part name only, that is, CFG845, CFG847, or CFG848.
SFR Address:
AFH
Power-On Default:
00H
Bit Addressable:
No
Table 7. CFG845/CFG847/CFG848 SFR Bit Designations
Bit No.
Name
Description
7
EXSP
Extended SP Enable.
If this bit is set to 1, the stack rolls over
from SPH/SP = 00FFH to 0100H.
If this bit is cleared to 0, SPH SFR is
disabled and the stack rolls over from
SP = FFH to SP = 00H.
6
----
Not Implemented. Write Don’t Care.
5
----
Not Implemented. Write Don’t Care.
4
----
Not Implemented. Write Don’t Care.
3
----
Not Implemented. Write Don’t Care.
----
Not Implemented. Write Don’t Care.
1
----
Not Implemented. Write Don’t Care.
0
XRAMEN
If this bit is set to 1, the internal XRAM is
mapped into the lower 2 kbytes of the
external address space.
If this bit is cleared to 0, the internal XRAM
is accessible and up to 16 MB of external
data memory become available. See
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