參數(shù)資料
型號(hào)： ADUC847BCPZ8-5
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 71/108頁(yè)
文件大?。?/td> 0K
描述： IC MCU FLASH W/24BIT ADC 56-CSP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x24b; D/A 1x12b，2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
包裝： 托盤
配用： EVAL-ADUC847QSZ-ND - KIT DEV QUICK START FOR ADUC847
Data Sheet
ADuC845/ADuC847/ADuC848
Rev. C | Page 65 of 108
SPICON—SPI Control Register
SFR Address:
F8H
Power-On Default:
05H
Bit Addressable:
Yes
Table 41. SPICON SFR Bit Designations
Bit No.
Name
Description
7
ISPI
SPI Interrupt Bit.
Set by the MicroConverter at the end of each SPI transfer.
Cleared directly by user code or indirectly by reading the SPIDAT SFR.
6
WCOL
Write Collision Error Bit.
Set by the MicroConverter if SPIDAT is written to while an SPI transfer is in progress.
Cleared by user code.
5
SPE
SPI Interface Enable Bit.
Set by user code to enable SPI functionality.
Cleared by user code to enable standard Port 2 functionality.
4
SPIM
SPI Master/Slave Mode Select Bit.
Set by user code to enable master mode operation (SCLOCK is an output).
Cleared by user code to enable slave mode operation (SCLOCK is an input).
3
CPOL1
Clock Polarity Bit.
Set by user code to enable SCLOCK idle high.
Cleared by user code to enable SCLOCK idle low.
2
Clock Phase Select Bit.
Set by user code if the leading SCLOCK edge is to transmit data.
Cleared by user code if the trailing SCLOCK edge is to transmit data.
1, 0
SPR1, SPR0
SPI Bit-Rate Bits.
SPR1
SPR0
Selected Bit Rate
0
fcore/2
0
1
fcore/4
1
0
fcore/8
1
fcore/16
1
The CPOL and CPHA bits should both contain the same values for master and slave devices.
Note that both SPI and I2C use the same ISR (Vector Address 3BH); therefore, when using SPI and I2C simultaneously, it is necessary to
check the interfaces following an interrupt to determine which one caused the interrupt.
SPIDAT: SPI Data Register
SFR Address:
7FH
Power-On Default:
00H
Bit Addressable:
No
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