參數(shù)資料
型號: ADUC842
廠商: Analog Devices, Inc.
元件分類: ADC
英文描述: CON, RTANG 68 POS
中文描述: 12 -位ADC和DAC的嵌入式高新技術(shù)高速62KB閃存微控制器
文件頁數(shù): 8/18頁
文件大?。?/td> 217K
代理商: ADUC842
Rev.PrB
ADuC842
–8–
Mnemonic
T ype F unction
PSE N
O
Program Store Enable, Logic Output. T his output is a control signal that enables the external
program memory to the bus during external fetch operations. It is active every six oscillator
periods except during external data memory accesses. T his pin remains high during internal
program execution. PSEN can also be used to enable serial download mode when pulled low
through a resistor on power-up or RESET .
Address Latch Enable, Logic Output. T his output is used to latch the low byte (and page byte for
24-bit address space accesses) of the address into external memory during normal operation.
External Access Enable, Logic Input. When held high, this input enables the device to fetch code
from internal program memory locations 0000H to 1FFFH. When held low this input enables the
device to fetch all instructions from external program memory. T his pin should not be left float.
Port 0 is an 8-Bit Open Drain Bidirectional I/O port. Port 0 pins that have 1s written to them
float and in that state can be used as high impedance inputs. Port 0 is also the multiplexed low
order address and data bus during accesses to external program or data memory. In this
application it uses strong internal pull-ups when emitting 1s.
A L E
O
E A
I
P0.7–P0.0
I/O
T E RMINOLOGY
A D C SP E C IF IC A T IONS
Integral Nonlinearity
T his is the maximum deviation of any code from a straight
line passing through the endpoints of the ADC transfer
function. T he endpoints of the transfer function are zero
scale, a point 1/2 LSB below the first code transition and
full scale, a point 1/2 LSB above the last code transition.
D ifferential Nonlinearity
T his is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the
AD C .
Offset E rror
T his is the deviation of the first code transition
(0000 . . . 000) to (0000 . . . 001) from the ideal, i.e., +1/2
L SB.
Gain E rror
T his is the deviation of the last code transition from the
ideal AIN voltage (Full Scale – 1.5 LSB) after the offset
error has been adjusted out.
Signal to (Noise + Distortion) Ratio
T his is the measured ratio of signal to (noise + distortion)
at the output of the A/D converter. T he signal is the rms
amplitude of the fundamental. Noise is the rms sum of all
nonfundamental signals up to half the sampling frequency
(f
S
/2), excluding dc. T he ratio is dependent upon the
number of quantization levels in the digitization process;
the more levels, the smaller the quantization noise. T he
theoretical signal to (noise +distortion) ratio for an ideal
N-bit converter with a sine wave input is given by:
Signal to
(
Noise + Distortion
)
=
(6.02
N
+ 1.76)
dB
T hus for a 12-bit converter, this is 74 dB.
T otal H armonic D istortion
T otal Harmonic Distortion is the ratio of the rms sum of
the harmonics to the fundamental.
D A C SP E C IF IC A T IONS
R elative A ccuracy
Relative accuracy or endpoint linearity is a measure of
the maximum deviation from a straight line passing
through the endpoints of the DAC transfer function. It is
measured after adjusting for zero error and full-scale er-
ror.
Voltage Output Settling T ime
T his is the amount of time it takes for the output to settle
to a specified level for a full-scale input change.
D igital-to-A nalog Glitch Impulse
T his is the amount of charge injected into the analog out-
put when the inputs change state. It is specified as the area
of the glitch in nV sec.
PIN F UNC T ION D E SC R IPT ION (continued)
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