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參數(shù)資料
| 型號： | ADUC842 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | CON, RTANG 68 POS |
| 中文描述： | 12 -位ADC和DAC的嵌入式高新技術(shù)高速62KB閃存微控制器 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大小： | 217K |
| 代理商： | ADUC842 |
Rev.PrB
ADuC842
T he main features of the MicroConverter I
2
C interface are:
–16–
- Only two bus lines are required; a serial data line
(SDATA) and a serial clock line (SC L OC K ).
- An I
2
C master can communicate with multiple slave
devices. Because each slave device has a unique 7-bit
address then single master/slave relationships can exist
at all times even in a multi slave environment
- Ability to respond to 4 seperate addresses when operat-
ing in slave mode
- An I
2
C slave can respond to repeated start conditions
without a stop bit in between. T his allows a master to
change direction of transfer without giving up the bus.
- On-C hip filtering rejects <50ns spikes on the SDATA
and the SCL OCK lines to preserve data integrity.
I
2
C
MASTER
I
2
C
SLAVE#2
I
2
C
SLAVE#1
DV
DD
Figure 36. Typical I
2
C System
Software Master Mode
T he ADuC841 can be used as a I
2
C master device by config-
uring the I
2
C peripheral in master mode and writing sotware
to output the data bit by bit. T his is referred to as a software
master. Master mode is enabled by setting the I2CM bit in
the I2CCON register.
T o transmit data on the SDAT A line, MDE must be set to
enable the output driver on the SDAT A pin. If MDE is set
then the SDAT A pin will be pulled high or low depending
on whether the MDO bit is set or cleared. MCO controls the
SCLOCK pin and is always configured as an output in mas-
ter mode. In master mode the SCLOCK pin will be pulled
high or low depending on the whether MCO is set or
cleared.
T o receive data, MDE must be cleared to disable the output
driver on SDAT A. Software must provide the clocks by tog-
gling the MCO bit and read SDAT A pin via the MDI bit. If
MDE is cleared MDI can be used to read the SDAT A pin.
T he value of the SDAT A pin is latched into MDI on a rising
edge pf SCLOCK . MDI is set if the SDAT A pin was high
on the last rising edge of SCLOCK . MDI is clear if the
SDAT A pin was low on the last rising edge of SCLOCK .
Software must control MDO, MCO and MDE appropri-
ately to generate the ST ART condition, slave address,
acknowledge bits, data bytes and ST OP conditions appro-
priately. T hese functions are provided in tech note uC001.
Hardware Slave Mode
After reset the ADuC842 defaults to hardware slave mode.
T he I
2
C interface is enabled by clearing the SPE bit in
SPICON. Slave mode is enabled by clearing the I2CM bit
in I2CCON. T he ADuC842 has a full hardware slave. In
slave mode the I
2
C address is stored in the I2CADD regis-
ter. Data received or to be transmitted is stored in the
I2CDAT register.
Once enabled in I
2
C slave mode the slave controller waits for
a ST ART condition. If the ADuC842 detects a valid start
condition, followed by a valid address, followed by the R/
bit the I2CI interrupt bit will get automatically set by hard-
ware.
T he I
2
C peripheral will only generate a core interrupt if the
user has pre-configured the I
2
C interrupt enable bit in the
IEIP2 SFR as well as the global interrupt bit EA in the IE
SFR. i.e.
; Enabling I2C Interrupts for the ADuC831
MOV IEIP2,#01h ; enable I2C interrupt
SETB EA
On the ADuC841 an auto-clear of the I2CI bit is imple-
mented so this bit is cleared automatically on a read or write
access to the I2CDAT SFR.
MOV I2CDAT, A ; I2CI auto-cleared
MOV A, I2CDAT ; I2CI auto-cleared
If for any reason the user tries to clear the interrupt more
than once i.e. access the data SFR more than once per inter-
rupt then the I
2
C controller will halt. T he interface will then
have to be reset using the I2CRS bit.
T he user can choose to poll the I2CI bit or enable the inter-
rupt. In the case of the interrupt the PC counter will vector
to 003BH at the end of each complete byte. For the first byte
when the user gets to the I2CI ISR the 7-bit address and the
R/ bit will appear in the I2CDAT SFR.
T he I2CT X bit contains the R/ bit sent from the master.
If I2CT X is set then the master would like to receive a byte.
Hence the slave will transmit data by writing to the I2CDAT
register. If I2CT X is cleared the master would like to trans-
mit a byte. Hence the slave will receive a serial byte.
Software can interrogate the state of I2CT X to determine
whether is should write to or read from I2CDAT .
Once the ADuC842 has received a valid address, hardware
will hold SCLOCK low until the I2CI bit is cleared by soft-
ware. T his allows the master to wait for the slave to be ready
before transmitting the clocks for the next byte.
T he I2CI interrupt bit will be set every time a complete data
byte is received or transmitted provided it is followed by a
valid ACK . If the byte is followed by a NACK an interrupt is
NOT generated. T he ADuC842 will continue to issue inter-
rupts for each complete data byte transferred until a ST OP
condition is received or the interface is reset.
When a ST OP condition is received, the interface will reset
to a state where it is waiting to be addressed (idle). Simi-
larly, if the interface receives a NACK at the end of a
sequence it also returns to the default idle state. T he I2CRS
bit can be used to reset the I
2
C interface. T his bit can be
used to force the interface back to the default idle state.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ADUC842BCP | 制造商:AD 制造商全稱:Analog Devices 功能描述:12- Bit ADCs and DACs with Embedded Hi-Speed 62KB FLASH MCU |
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| ADUC842BCP62-3 | 制造商:Analog Devices 功能描述:MCU 8-bit ADuC8xx 8052 CISC 62KB Flash 3V 56-Pin LFCSP EP |
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