參數(shù)資料
型號: ADUC836
廠商: Analog Devices, Inc.
元件分類: 串行ADC
英文描述: MicroConverter, Dual 16-Bit-ADCs with Embedded 62 kB Flash MCU
中文描述: MicroConverter的,雙16位ADC的與嵌入62 kB閃存微控制器
文件頁數(shù): 36/80頁
文件大?。?/td> 5913K
代理商: ADUC836
ADuC836
–36–
PULSEWIDTH MODULATOR (PWM)
The PWM on the ADuC836 is a highly flexible PWM offering
programmable resolution and input clock, and can be configured
for any one of six different modes of operation. Two of these modes
allow the PWM to be configured as a
-
DAC with up to 16 bits
of resolution. A block diagram of the PWM is shown in Figure 26.
CLOCK
SELECT
PROGRAMMABLE
DIVIDER
COMPARE
MODE
PWM0H/L
12.583MHz
PWM
CLK
32.768kHz
32.768kHz/15
P1.0
P1.1
16-BIT PWM COUNTER
Figure 26. PWM Block Diagram
Table XVI. PWMCON SFR Bit Designations
Description
Reserved for Future Use
PWM Mode Bits
The MD2/1/0 bits choose the PWM mode as follows:
MD2
MD1
MD0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
PWM Clock Divider.
Scale the clock source for the PWM counter as follows:
CDIV1 CDIV0
Description
0
0
PWM Counter = Selected Clock/1
0
1
PWM Counter = Selected Clock 4
1
0
PWM Counter = Selected Clock/16
1
1
PWM Counter = Selected Clock/64
PWM Clock Divider.
Select the clock source for the PWM as follows:
CSEL1 CSEL0
Description
0
0
PWM Clock = f
XTAL
/15
0
1
PWM Clock = f
XTAL
1
0
PWM Clock = External Input at P3.4/T0/PWMCLK
1
1
PWM Clock = f
VCO
(12.58 MHz)
Bit
7
6
5
4
3
2
1
0
Name
–––
MD2
MD1
MD0
CDIV1
CDIV0
CSEL1
CSEL0
Mode
Mode 0: PWM Disabled
Mode 1: Single Variable Resolution PWM
Mode 2: Twin 8-bit PWM
Mode 3: Twin 16-bit PWM
Mode 4: Dual NRZ 16-bit
-
DAC
Mode 5: Dual 8-bit PWM
Mode 6: Dual RZ 16-bit
-
DAC
Reserved for Future Use
The PWM uses five SFRs: the control SFR, PWMCON, and
four data SFRs: PWM0H, PWM0L, PWM1H, and PWM1L.
PWMCON (as described in Table XVI) controls the different
modes of operation of the PWM as well as the PWM clock fre-
quency. PWM0H/L and PWM1H/L are the data registers that
determine the duty cycles of the PWM outputs at P1.0 and P1.1.
To use the PWM user software, first write to PWMCON to select
the PWM mode of operation and the PWM input clock. Writing
to PWMCON also resets the PWM counter. In any of the 16-bit
modes of operation (modes 1, 3, 4, 6), user software should write
to the PWM0L or PWM1L SFRs first. This value is written to a
hidden SFR. Writing to the PWM0H or PWM1H SFRs updates
both the PWMxH and the PWMxL SFRs but does not change
the outputs until the end of the PWM cycle in progress. The
values written to these 16-bit registers are then used in the next
PWM cycle.
PWMCON PWM Control SFR
SFR Address AEH
Power-On Default Value 00H
Bit Addressable No
REV. A
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