參數(shù)資料
型號: ADUC832BCPZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 29/92頁
文件大?。?/td> 0K
描述: IC MCU 62K FLASH ADC/DAC 56LFCSP
標準包裝: 2,500
系列: MicroConverter® ADuC8xx
核心處理器: 8052
芯體尺寸: 8-位
速度: 16MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設備: PSM,溫度傳感器,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 62KB(62K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 4K x 8
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據轉換器: A/D 8x12b,D/A 2x12b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
包裝: 帶卷 (TR)
Data Sheet
ADuC832
Rev. B | Page 35 of 92
ADC CIRCUIT INFORMATION
GENERAL OVERVIEW
The ADC conversion block incorporates a fast, 8-channel,
12-bit, single-supply ADC. This block provides the user with
multichannel mux, track/hold, on-chip reference, calibration
features, and an ADC. All components in this block are easily
configured via a three-register SFR interface.
The ADC consists of a conventional successive approximation
converter based around a capacitor DAC. The converter accepts
an analog input range of 0 V to VREF. A high precision, low drift,
and factory calibrated 2.5 V reference is provided on-chip. An
external reference can be connected as described in the Voltage
Reference Connections section. This external reference can be
in the range of 1 V to AVDD.
Single step or continuous conversion modes can be initiated in
software or alternatively by applying a convert signal to an
external pin. Timer 2 can also be configured to generate a
repetitive trigger for ADC conversions. The ADC can be
configured to operate in a DMA mode whereby the ADC block
continuously converts and captures samples to an external
RAM space without any interaction from the MCU core. This
automatic capture facility can extend through a 16 MB external
data memory space.
The ADuC832 is shipped with factory programmed calibration
coefficients that are automatically downloaded to the ADC on
power-up, ensuring optimum ADC performance. The ADC
core contains internal offset and gain calibration registers that
can be hardware calibrated to minimize system errors.
A voltage output from an on-chip band gap reference propor-
tional to absolute temperature can also be routed through the
front-end ADC multiplexer (effectively a ninth ADC channel
input) facilitating a temperature sensor implementation.
ADC TRANSFER FUNCTION
The analog input range for the ADC is 0 V to VREF. For this range,
the designed code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs…FS
3/2 LSBs). The output coding is straight binary with 1 LSB =
FS/4096 or 2.5 V/4096 = 0.61 mV when VREF = 2.5 V. The ideal
input/output transfer characteristic for the 0 V to VREF range is
shown in Figure 37.
OUTPUT
CODE
111...111
111...110
111...101
111...100
000...011
000...010
000...001
000...000
0V 1LSB
+FS
–1LSB
VOLTAGE INPUT
1LSB =
FS
4096
02987-
026
Figure 37. ADC Transfer Function
TYPICAL OPERATION
Once configured via the ADCCON1 to ADCCON3 SFRs, the
ADC converts the analog input and provides an ADC 12-bit
result word in the ADCDATAH/ADCDATAHL SFRs. The top
four bits of the ADCDATAH SFR are written with the channel
selection bits to identify the channel result. The format of the ADC
12-bit result word is shown in Figure 38.
CH–ID
TOP 4 BITS
HIGH 4 BITS OF
ADC RESULT WORD
LOW 8 BITS OF THE
ADC RESULT WORD
ADCDATAH SFR
ADCDATAL SFR
02987-
027
Figure 38. ADC Result Format
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