參數(shù)資料
型號： ADUC831BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 37/76頁
文件大?。?/td> 0K
描述： IC MCU 62K FLASH ADC/DAC 56LFCSP
標準包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 16MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設備： PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 62KB（62K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
包裝： 托盤
配用： EVAL-ADUC831QSZ-ND - KIT DEV FOR ADUC831 QUICK START
REV. 0
–42–
ADuC831
Table XIII. DPCON SFR Bit Designations
Bit
Name
Description
7
----
Reserved for Future Use.
6
DPT
Data Pointer Automatic Toggle Enable.
Cleared by user to disable auto swapping of the DPTR.
Set in user software to enable automatic toggling of the DPTR after each MOVX or MOVC instruction.
5DP1m1
Shadow Data Pointer Mode.
4DP1m0
These two bits enable extra modes of the shadow data pointer operation, allowing for more compact
and more efficient code size and execution.
m1
m0
Behavior of the Shadow Data Pointer
00
8052 Behavior
01
DPTR is post-incremented after a MOVX or a MOVC instruction.
10
DPTR is post-decremented after a MOVX or MOVC instruction.
11
DPTR LSB is toggled after a MOVX or MOVC instruction.
(This instruction can be useful for moving 8-bit blocks to/from 16-bit devices.)
3DP0m1
Main Data Pointer Mode.
2DP0m0
These two bits enable extra modes of the main data pointer operation, allowing for more compact and
more efficient code size and execution.
m1
m0
Behavior of the Main Data Pointer
00
8052 Behavior
01
DPTR is post-incremented after a MOVX or a MOVC instruction.
10
DPTR is post-decremented after a MOVX or MOVC instruction.
11
DPTR LSB is toggled after a MOVX or MOVC instruction.
(This instruction can be useful for moving 8-bit blocks to/from 16-bit devices.)
1This bit is not implemented to allow the INC DPCON instruction toggle the data pointer without
incrementing the rest of the SFR.
0
DPSEL
Data Pointer Select.
Cleared by user to select the main data pointer. This means that the contents of this 24-bit register
is placed into the three SFRs DPL, DPH, and DPP.
Set by the user to select the shadow data pointer. This means that the contents of a separate 24-bit
register appears in the three SFRs DPL, DPH, and DPP.
DUAL DATA POINTER
The ADuC831 incorporates two data pointers. The second data
pointer is a shadow data pointer and is selected via the data
pointer control SFR (DPCON). DPCON also includes some
nice features such as automatic hardware post-increment and
post-decrement as well as automatic data pointer toggle.
DPCON is described in Table XIII.
DPCON
Data Pointer Control SFR
SFR Address
A7H
Power-On Default Value
00H
Bit Addressable
No
Note 1: This is the only place where the main and shadow data
pointers are distinguished. Everywhere else in this data sheet
wherever the DPTR is mentioned, operation on the active
DPTR is implied.
Note 2: Only MOVC/MOVX @DPTR instructions are relevant
above. MOVC/MOVX PC/@Ri instructions will not cause the
DPTR to automatically post increment/decrement, and so on.
To illustrate the operation of DPCON, the following code will
copy 256 bytes of code memory at address D000H into XRAM
starting from address 0000H.
The following code uses 16 bytes and 2054 cycles. To perform
this on a standard 8051 requires approximately 33 bytes and
7172 cycles (depending on how it is implemented).
MOV
DPTR,#0
; Main DPTR = 0
MOV
DPCON,#55H
; Select shadow DPTR
; DPTR1 increment mode,
; DPTR0 increment mode
; DPTR auto toggling ON
MOV
DPTR,#0D000H
; Shadow DPTR = D000H
MOVELOOP:
CLR
A
MOVC A,@A+DPTR
; Get data
; Post Inc DPTR
; Swap to Main DPTR (Data)
MOVX @DPTR,A
; Put ACC in XRAM
; Increment main DPTR
; Swap Shadow DPTR (Code)
MOV
A, DPL
JNZ
MOVELOOP
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