參數(shù)資料
型號: ADUC831BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 14/76頁
文件大?。?/td> 0K
描述: IC MCU 62K FLASH ADC/DAC 56LFCSP
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC8xx
核心處理器: 8052
芯體尺寸: 8-位
速度: 16MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: PSM,溫度傳感器,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 62KB(62K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
包裝: 托盤
配用: EVAL-ADUC831QSZ-ND - KIT DEV FOR ADUC831 QUICK START
REV. 0
ADuC831
–21–
Table V. ADCCON3 SFR Bit Designations
Bit
Name
Description
ADCCON3.7 BUSY
The ADC Busy Status Bit (BUSY) is a read-only status bit that is set during a valid ADC conversion or
calibration cycle. Busy is automatically cleared by the core at the end of conversion or calibration.
ADCCON3.6 GNCLD
Gain Calibration Disable Bit
Set to “0” to Enable Gain Calibration.
Set to “1” to Disable Gain Calibration.
ADCCON3.5 AVGS1
Number of Averages Selection Bits
ADCCON3.4 AVGS0
This bit selects the number of ADC readings averaged during a calibration cycle.
AVGS1
AVGS0
Number of Averages
0
15
0
1
0
31
1
63
ADCCON3.3 RSVD
Reserved. This bit should always be written as “0.”
ADCCON3.2 RSVD
This bit should always be written as “1” by the user when performing calibration.
ADCCON3.1 TYPICAL
Calibration Type Select Bit.
This bit selects between Offset (zero-scale) and gain (full-scale) calibration.
Set to 0 for Offset Calibration.
Set to 1 for Gain Calibration.
ADCCON3.0 SCAL
Start Calibration Cycle Bit.
When set, this bit starts the selected calibration cycle. It is automatically cleared when the calibration
cycle is completed.
ADCCON3 – (ADC Control SFR #3)
The ADCCON3 register controls the operation of various calibra-
tion modes as well as giving an indication of ADC busy status.
SFR Address:
F5H
SFR Power-On Default Value:
00H
Bit Addressable:
NO
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