DVDD P Digital Positive Supply Voltage" />
參數(shù)資料
型號(hào)： ADUC812BSZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 55/57頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT MULTICH MCU 52-MQFP
產(chǎn)品培訓(xùn)模塊： Process Control
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 16MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大小： 640 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 52-QFP
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 738 (CN2011-ZH PDF)
REV.
ADuC812
–7–
PIN FUNCTION DESCRIPTIONS
Mnemonic
Type
Function
DVDD
P
Digital Positive Supply Voltage, 3 V or 5 V Nominal.
AVDD
P
Analog Positive Supply Voltage, 3 V or 5 V Nominal.
CREF
I
Decoupling Input for On-Chip Reference. Connect 0.1 μF between this pin and AGND.
VREF
I/O
Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the
reference source for the ADC. The nominal internal reference voltage is 2.5 V, which appears at the pin.
This pin can be overdriven by an external reference.
AGND
G
Analog Ground. Ground reference point for the analog circuitry.
P1.0–P1.7
I
Port 1 is an 8-bit input port only. Unlike other ports, Port 1 defaults to Analog Input mode. To configure
any of these Port Pins as a digital input, write a 0 to the port bit. Port 1 pins are multifunctional and share
the following functionality.
ADC0–ADC7
I
Analog Inputs. Eight single-ended analog inputs. Channel selection is via ADCCON2 SFR.
T2
I
Timer 2 Digital Input. Input to Timer/Counter 2. When enabled, Counter 2 is incremented in response to a
1 to 0 transition of the T2 input.
T2EX
I
Digital Input. Capture/Reload trigger for Counter 2; also functions as an Up/Down control input for
Counter 2.
SS
I
Slave Select Input for the SPI Interface.
SDATA
I/O
User selectable, I
2C Compatible or SPI Data Input/Output Pin.
SCLOCK
I/O
Serial Clock Pin for I
2C Compatible or SPI Serial Interface Clock.
MOSI
I/O
SPI Master Output/Slave Input Data I/O Pin for SPI Interface.
MISO
I/O
SPI Master Input/Slave Output Data I/O Pin for SPI Serial Interface.
DAC0
O
Voltage Output from DAC0.
DAC1
O
Voltage Output from DAC1.
RESET
I
Digital Input. A high level on this pin for 24 master clock cycles while the oscillator is running resets the
device. External power-on reset (POR) circuity must be implemented to drive the RESET pin as described
in the Power-On Reset Operation section.
P3.0–P3.7
I/O
Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are
pulled high by the internal pull-up resistors; in that state they can be used as inputs. As inputs, Port 3 pins
being pulled externally low will source current because of the internal pull-up resistors. Port 3 pins also
contain various secondary functions that are described below.
RxD
I/O
Receiver Data Input (Asynchronous) or Data Input/Output (Synchronous) of Serial (UART) Port
TxD
O
Transmitter Data Output (Asynchronous) or Clock Output (Synchronous) of Serial (UART) Port
INT0
I
Interrupt 0, programmable edge or level triggered Interrupt input,
INT0 can be programmed to one of two
priority levels. This pin can also be used as a gate control input to Timer 0.
INT1
I
Interrupt 1, programmable edge or level triggered Interrupt input,
INT1 can be programmed to one of two
priority levels. This pin can also be used as a gate control input to Timer 1.
T0
I
Timer/Counter 0 Input.
T1
I
Timer/Counter 1 Input.
CONVST
I
Active Low Convert Start Logic Input for the ADC Block when the External Convert Start Function is Enabled.
A low-to-high transition on this input puts the track-and-hold into its hold mode and starts conversion.
WR
O
Write Control Signal, Logic Output. Latches the data byte from Port 0 into the external data memory.
RD
O
Read Control Signal, Logic Output. Enables the external data memory to Port 0.
XTAL2
O
Output of the Inverting Oscillator Amplifier.
XTAL1
I
Input to the Inverting Oscillator Amplifier and to the Internal Clock Generator Circuits.
DGND
G
Digital Ground. Ground reference point for the digital circuitry.
P2.0–P2.7
I/O
Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are
(A8–A15)
pulled high by the internal pull-up resistors; in that state they can be used as inputs. As inputs, Port 2
(A16–A23)
pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 emits the
high order address bytes during fetches from external program memory and middle and high order address
bytes during accesses to the external 24-bit external data memory space.
F
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