user can help keep AVDD
參數(shù)資料
型號(hào)： ADUC812BSZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 37/57頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT MULTICH MCU 52-MQFP
產(chǎn)品培訓(xùn)模塊： Process Control
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 16MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
EEPROM 大小： 640 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 52-QFP
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 738 (CN2011-ZH PDF)
REV.
ADuC812
–42–
As an alternative to providing two separate power supplies, the
user can help keep AVDD quiet by placing a small series resistor
and/or ferrite bead between it and DVDD, and then decoupling
AVDD separately to ground. An example of this configuration is
shown in Figure 44. With this configuration, other analog
circuitry (such as op amps, voltage reference, and so on) can be
powered from the AVDD supply line as well. The user will still
want to include back-to-back Schottky diodes between AVDD
and DVDD in order to protect from power-up and power-down
transient conditions that could separate the two supply voltages
momentarily.
DVDD
48
34
20
ADuC812
5
6
AGND
AVDD
0.1 F
10 F
DGND
35
21
47
0.1 F
–
+
DIGITAL SUPPLY
10 F
1.6
BEAD
Figure 44. External Single-Supply Connections
Notice that in both Figure 43 and Figure 44, a large value (10 μF)
reservoir capacitor sits on DVDD and a separate 10 μF capacitor
sits on AVDD. Also, local small value (0.1 μF) capacitors are
located at each VDD pin of the chip. As per standard design prac-
tice, be sure to include all of these capacitors, and ensure the
smaller capacitors are close to each AVDD pin with trace lengths as
short as possible. Connect the ground terminal of each of these
capacitors directly to the underlying ground plane. Finally, it
should also be noted that, at all times, the analog and digital
ground pins on the ADuC812 must be referenced to the same
system ground reference point.
Power Consumption
The currents consumed by the various sections of the ADuC812
are shown in Table XXVII. The CORE values given represent
the current drawn by DVDD, while the rest (ADC, DAC, Volt-
age Reference) are pulled by the AVDD pin and can be disabled
in software when not in use. The other on-chip peripherals
(watchdog timer, power supply monitor, and so on) consume
negligible current and are therefore lumped in with the CORE
operating current here. Of course, the user must add any
currents sourced by the DAC or the parallel and serial I/O pins,
in order to determine the total current needed at the ADuC812’s
supply pins. Also, current drawn from the DVDD supply will
increase by approximately 10 mA during Flash/EE erase and
program cycles.
Table XXVII. Typical IDD of Core and Peripherals
VDD = 5 V
VDD = 3 V
CORE
(Normal Mode) (1.6 nAs
× MCLK) + (0.8 nAs × MCLK) +
6 mA
3 mA
CORE
(Idle Mode)
(0.75 nAs
× MCLK) + (0.25 nAs × MCLK) +
5 mA
3 mA
ADC
1.3 mA
1.0 mA
DAC (Each)
250 μA
200 μA
Voltage Ref
200 μA
150 μA
Since operating DVDD current is primarily a function of clock
speed, the expressions for CORE supply current in Table XXVII
are given as functions of MCLK, the oscillator frequency. Plug
in a value for MCLK in hertz to determine the current consumed
by the core at that oscillator frequency. Since the ADC and DACs
can be enabled or disabled in software, add only the currents
from the peripherals you expect to use. The internal voltage refer-
ence is automatically enabled whenever either the ADC or at
least one DAC is enabled. And again, do not forget to include
current sourced by I/O pins, serial port pins, DAC outputs, and
so forth, plus the additional current drawn during Flash/EE
erase and program cycles.
A software switch allows the chip to be switched from normal
mode into idle mode, and also into full power-down mode.
Below are brief descriptions of power-down and idle modes.
In idle mode, the oscillator continues to run but is gated off to
the core only. The on-chip peripherals continue to receive the
clock, and remain functional. Port pins and DAC output pins
retain their states in this mode. The chip will recover from idle
mode upon receiving any enabled interrupt, or upon receiving a
hardware reset.
In full power-down mode, the on-chip oscillator stops, and all
on-chip peripherals are shut down. Port pins retain their logic levels
in this mode, but the DAC output goes to a high impedance
state (three-state). The chip will only recover from power-down
mode upon receiving a hardware reset or when power is cycled.
During full power-down mode, the ADuC812 consumes a total
of approximately 5 μA.
F
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