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參數(shù)資料
| 型號： | ADUC7129BSTZ126-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 83/92頁 |
| 文件大小： | 0K |
| 描述： | IC DAS MCU ARM7 ADC/DDS 80-LQFP |
| 產(chǎn)品培訓模塊： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters Process Control Direct Digital Synthesis Tutorial Series (1 of 7): Introduction |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設備： | PLA，POR，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 38 |
| 程序存儲器容量： | 126KB（63K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x12b; D/A 1x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 80-LQFP |
| 包裝： | 標準包裝 |
| 其它名稱： | ADUC7129BSTZ126-RLDKR |
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ADuC7128/ADuC7129
Rev. 0 | Page 84 of 92
The XMxPAR are registers that define the protocol used for accessing the external memory for each memory region.
Table 121. XMxPAR MMR Bit Designations
Bit
Description
15
Enable Byte Write Strobe. This bit is only used for two,
8-bit memory sharing the same memory region.
Set by user to gate the AD0 output with the WS output. This allows byte write capability without using BHE and BLE signals.
Cleared by user to use BHE and BLE signals.
14:12
Number of Wait States on the Address Latch Enable Strobe.
11
Reserved.
10
Extra Address Hold Time.
Set by the user to disable extra hold time.
Cleared by the user to enable one clock cycle of hold on the address in read and write.
9
Extra Bus Transition Time on Read.
Set by the user to disable extra bus transition time.
Cleared by the user to enable one extra clock before and after the read select (RS).
8
Extra Bus Transition Time on Write.
Set by the user to disable extra bus transition time.
Cleared by the user to enable one extra clock before and after the write select (WS).
7:4
Number of Write Wait States. Select the number of wait states added to the length of the WS pulse. 0x0 is 1 clock cycle; 0xF is 16 clock
cycles (default value).
3:0
Number of Read Wait States. Select the number of wait states added to the length of the RS pulse. 0x0 is 1 clock cycle; 0xF is 16 clock
cycles (default value).
TIMING DIAGRAMS
Figure 62 through Figure 65 show the timing for a read cycle (see Figure 62), a read cycle with address hold and bus turn cycles (see
Figure 63), a write cycle with address hold and write hold cycles (see Figure 64), and a write cycle with wait states (see Figure 65).
06
02
0-
06
9
HCLK
AD16:0
ADDRESS
DATA
MSx
AE
RS
Figure 62. External Memory Read Cycle
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