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| 型號： | ADUC7129BSTZ126-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 53/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS MCU ARM7 ADC/DDS 80-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters Process Control Direct Digital Synthesis Tutorial Series (1 of 7): Introduction |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PLA，POR，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 38 |
| 程序存儲器容量： | 126KB（63K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x12b; D/A 1x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 80-LQFP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADUC7129BSTZ126-RLDKR |
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ADuC7128/ADuC7129
Rev. 0 | Page 57 of 92
GPxDAT Register
Name
Address
Default Value
Access
GP0DAT
0xFFFF0D20
0x000000XX
R/W
GP1DAT
0xFFFF0D30
0x000000XX
R/W
GP2DAT
0xFFFF0D40
0x000000XX
R/W
GP3DAT
0xFFFF0D50
0x000000XX
R/W
GP4DAT
0xFFFF0D60
0x000000XX
R/W
GPxDAT is a Port x configuration and data register. It configures
the direction of the GPIO pins of Port x, sets the output value
for the pins configured as output, and receives and stores the
input value of the pins configured as input.
Table 73. GPxDAT MMR Bit Designations
Bit
Description
31:24
Direction of the Data.
Set to 1 by user to configure the GPIO pins as outputs.
Cleared to 0 by user to configure the GPIO pins as
inputs.
23:16
Port x Data Output.
15:8
Reflect the state of Port x pins at reset (read only).
7:0
Port x Data Input (Read Only).
GPxSET Register
Name
Address
Default Value
Access
GP0SET
0xFFFF0D24
0x000000XX
W
GP1SET
0xFFFF0D34
0x000000XX
W
GP2SET
0xFFFF0D44
0x000000XX
W
GP3SET
0xFFFF0D54
0x000000XX
W
GP4SET
0xFFFF0D64
0x000000XX
W
GPxSET is a data set Port x register.
Table 74. GPxSET MMR Bit Designations
Bit
Description
31:24
Reserved.
23:16
Data Port x Set Bit.
Set to 1 by user to set bit on Port x; also sets the
corresponding bit in the GPxDAT MMR.
Cleared to 0 by user; does not affect the data out.
15:0
Reserved.
GPxCLR Register
Name
Address
Default Value
Access
GP0CLR
0xFFFF0D28
0x000000XX
W
GP1CLR
0xFFFF0D38
0x000000XX
W
GP2CLR
0xFFFF0D48
0x000000XX
W
GP3CLR
0xFFFF0D58
0x000000XX
W
GP4CLR
0xFFFF0D68
0x000000XX
W
GPxCLR is a data clear Port x register.
Table 75. GPxCLR MMR Bit Designations
Bit
Description
31:24
Reserved.
23:16
Data Port x Clear Bit.
Set to 1 by user to clear bit on Port x; also clears
the corresponding bit in the GPxDAT MMR.
Cleared to 0 by user; does not affect the data out.
15:0
Reserved.
SERIAL PORT MUX
The serial port mux multiplexes the serial port peripherals (two
I2Cs, an SPI, and two UARTs) and the programmable logic array
(PLA) to a set of 10 GPIO pins. Each pin must be configured to
its specific I/O function as described in Table 76.
Table 76. SPM Configuration
Pin
GPIO
(00)
UART
(01)
UART/I2C/SPI
(10)
PLA
(11)
SPM0
P1.0
SIN0
I2C0SCL
PLAI[0]
SPM1
P1.1
SOUT0
I2C0SDA
PLAI[1]
SPM2
P1.2
RTS0
I2C1SCL
PLAI[2]
SPM3
P1.3
CTS0
I2C1SDA
PLAI[3]
SPM4
P1.4
RI0
SPICLK
PLAI[4]
SPM5
P1.5
DCD0
SPIMISO
PLAI[5]
SPM6
P1.6
DSR0
SPIMOSI
PLAI[6]
SPM7
P1.7
DTR0
SPICSL
PLAO[0]
SPM8
P0.7
ECLK
SIN0
PLAO[4]
SPM9
PWMSYNC
SOUT0
PLAO[5]
SPM10
RTS1
RS
PLAO[7]
SPM11
CTS1
AE
SPM12
RI1
MS0
SPM13
DCD1
MS1
SPM14
DSR1
MS2
SPM15
DTR1
MS3
SPM16
P4.6
SIN1
AD14
PLAO[14]
SPM17
P4.7
SOUT1
AD15
PLAO[15]
1 Available only on the 80-lead ADuC7129.
Table 76 details the mode for each of the SPMUX GPIO pins.
This configuration has to be performed via the GP0CON,
GP1CON and GP2CON MMRs. By default these pins are
configured as GPIOs.
UART SERIAL INTERFACE
The ADuC7128/ADuC7129 contain two identical UART
blocks. Although only UART0 is described here, UART1
functions in exactly the same way.
The UART peripheral is a full-duplex universal asynchronous
receiver/transmitter, fully compatible with the 16450 serial port
standard.
The UART performs serial-to-parallel conversion on data
characters received from a peripheral device or a modem, and
parallel-to-serial conversion on data characters received from
the CPU. The UART includes a fractional divider for baud rate
generation and has a network-addressable mode. The UART
function is made available on 10 pins of the ADuC7128/
ADuC7129 (see Table 77).
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