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| 型號： | ADUC7129BSTZ126-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 50/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS MCU ARM7 ADC/DDS 80-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters Process Control Direct Digital Synthesis Tutorial Series (1 of 7): Introduction |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PLA，POR，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 38 |
| 程序存儲器容量： | 126KB（63K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x12b; D/A 1x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 80-LQFP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADUC7129BSTZ126-RLDKR |
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ADuC7128/ADuC7129
Rev. 0 | Page 54 of 92
Table 68. QENCON MMR Bit Designations
Bit
Name
Description
15:11
RSVD
Reserved.
10
FILTEN
Set to 1 by the user to enable filtering on the S1 pin.
Cleared by user to disable filtering on the S1 pin.
9
RSVD
Reserved. This bit should be set to 0 by the user.
8
S2INV
Set to 1 by the user to invert the S2 input.
Cleared by user to use the S2 input as normal.
If the DIRCON bit is set, then S2INV controls the direction of the counter.
In this case, set to 1 by the user to operate the counter in increment mode.
Cleared by user to operate the counter in decrement mode.
7
S1INV
Set to 1 by the user to invert the S1 input.
Cleared by user to use the S1 input as normal.
6
DIRCON
Direction Control.
Set to 1 by the user to enable S1 as the input to the counter clock. The direction of the counter is controlled
via the S2INV bit.
Cleared by user to operate in normal mode.
5
S1IRQEN
Set to 1 by the user to generate an IRQ when a low-to-high transition is detected on S1.
Cleared by the user to disable the interrupt.
4
RSVD
This bit should be set to 0 by the user.
3
UIRQEN
Underflow IRQ Enable.
Set to 1 by the user to generate an interrupt if QENVAL underflows.
Cleared by the user to disable the interrupt.
2
OIREQEN
Overflow IRQ Enable.
Set to 1 by the user to generate an interrupt if QENVAL overflows.
Cleared by user to disable the interrupt.
1
RSVD
This bit should be set to 0 by the user.
0
ENQEN
Quadrature Encoder Enable.
Set to 1 by the user to enable the quadrature encoder.
Cleared by user to disable the quadrature encoder.
Table 69. QENSTA MMR Bit Designations
Bit
Name
Description
7:5
RSVD
Reserved.
4
S1EDGE
S1 Rising Edge.
This bit is set automatically on a rising edge of S1.
Cleared by reading QENSTA.
3
RSVD
Reserved.
2
UNDER
Underflow Flag.
This bit is set automatically if an underflow occurs.
Cleared by reading QENSTA.
1
OVER
This bit is set automatically if an overflow has occurred.
Cleared by reading QENSTA.
0
DIR
Direction of the Counter.
Set to 1 by hardware to indicate that the counter is incrementing.
Set to 0 by hardware to indicate that the counter is decrementing.
QENDAT Register
Name
Address
Default Value
Access
QENDAT
0xFFFF0F08
0Xffff
R/W
The QENDAT register holds the maximum value allowed for the
QENVAL register. If the QENVAL register increments past the
value in this register, an overflow condition occurs. When an over-
flow occurs, the QENVAL register is reset to 0x0000. When the
QENVAL register decrements past zero during an underflow,
it is loaded with the value in QENDAT.
QENVAL Register
Name
Address
Default Value
Access
QENVAL
0xFFFF0F0C
0x0000
R/W
The QENVAL register contains the current value of the quadrature
encoder counter.
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